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authorIan Romanick <idr@us.ibm.com>2007-07-26 16:58:28 -0700
committerIan Romanick <idr@us.ibm.com>2007-07-26 16:58:28 -0700
commitc561cb4650dc5895acfb3ae00c7ff455be31a860 (patch)
tree65b21097253d216e0385778597031ae288e34023 /shared-core/nv20_graph.c
parent2bafeb673f14b1e3799bf00817138c0b8211635e (diff)
parent4175dd818110bd10d6d09190d30c271e89202b18 (diff)
Merge branch 'master' of ssh+git://git.freedesktop.org/git/mesa/drm into xgi-0-0-2
Conflicts: linux-core/drmP.h linux-core/drm_scatter.c
Diffstat (limited to 'shared-core/nv20_graph.c')
-rw-r--r--shared-core/nv20_graph.c47
1 files changed, 25 insertions, 22 deletions
diff --git a/shared-core/nv20_graph.c b/shared-core/nv20_graph.c
index 06d7e440..1670c527 100644
--- a/shared-core/nv20_graph.c
+++ b/shared-core/nv20_graph.c
@@ -29,9 +29,9 @@
#define NV20_GRCTX_SIZE (3529*4)
-int nv20_graph_create_context(drm_device_t *dev, int channel) {
- drm_nouveau_private_t *dev_priv =
- (drm_nouveau_private_t *)dev->dev_private;
+int nv20_graph_create_context(struct drm_device *dev, int channel) {
+ struct drm_nouveau_private *dev_priv =
+ (struct drm_nouveau_private *)dev->dev_private;
struct nouveau_fifo *chan = dev_priv->fifos[channel];
unsigned int ctx_size = NV20_GRCTX_SIZE;
int ret;
@@ -49,8 +49,8 @@ int nv20_graph_create_context(drm_device_t *dev, int channel) {
return 0;
}
-void nv20_graph_destroy_context(drm_device_t *dev, int channel) {
- drm_nouveau_private_t *dev_priv = dev->dev_private;
+void nv20_graph_destroy_context(struct drm_device *dev, int channel) {
+ struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nouveau_fifo *chan = dev_priv->fifos[channel];
if (chan->ramin_grctx)
@@ -59,9 +59,9 @@ void nv20_graph_destroy_context(drm_device_t *dev, int channel) {
INSTANCE_WR(dev_priv->ctx_table->gpuobj, channel, 0);
}
-static void nv20_graph_rdi(drm_device_t *dev) {
- drm_nouveau_private_t *dev_priv =
- (drm_nouveau_private_t *)dev->dev_private;
+static void nv20_graph_rdi(struct drm_device *dev) {
+ struct drm_nouveau_private *dev_priv =
+ (struct drm_nouveau_private *)dev->dev_private;
int i;
NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x2c80000);
@@ -73,15 +73,15 @@ static void nv20_graph_rdi(drm_device_t *dev) {
/* Save current context (from PGRAPH) into the channel's context
*/
-int nv20_graph_save_context(drm_device_t *dev, int channel) {
- drm_nouveau_private_t *dev_priv =
- (drm_nouveau_private_t *)dev->dev_private;
+int nv20_graph_save_context(struct drm_device *dev, int channel) {
+ struct drm_nouveau_private *dev_priv =
+ (struct drm_nouveau_private *)dev->dev_private;
struct nouveau_fifo *chan = dev_priv->fifos[channel];
uint32_t instance;
instance = INSTANCE_RD(dev_priv->ctx_table->gpuobj, channel);
if (!instance) {
- return DRM_ERR(EINVAL);
+ return -EINVAL;
}
if (instance != (chan->ramin_grctx->instance >> 4))
DRM_ERROR("nv20_graph_save_context : bad instance\n");
@@ -94,15 +94,15 @@ int nv20_graph_save_context(drm_device_t *dev, int channel) {
/* Restore the context for a specific channel into PGRAPH
*/
-int nv20_graph_load_context(drm_device_t *dev, int channel) {
- drm_nouveau_private_t *dev_priv =
- (drm_nouveau_private_t *)dev->dev_private;
+int nv20_graph_load_context(struct drm_device *dev, int channel) {
+ struct drm_nouveau_private *dev_priv =
+ (struct drm_nouveau_private *)dev->dev_private;
struct nouveau_fifo *chan = dev_priv->fifos[channel];
uint32_t instance;
instance = INSTANCE_RD(dev_priv->ctx_table->gpuobj, channel);
if (!instance) {
- return DRM_ERR(EINVAL);
+ return -EINVAL;
}
if (instance != (chan->ramin_grctx->instance >> 4))
DRM_ERROR("nv20_graph_load_context_current : bad instance\n");
@@ -113,9 +113,9 @@ int nv20_graph_load_context(drm_device_t *dev, int channel) {
return 0;
}
-void nouveau_nv20_context_switch(drm_device_t *dev)
+void nouveau_nv20_context_switch(struct drm_device *dev)
{
- drm_nouveau_private_t *dev_priv = dev->dev_private;
+ struct drm_nouveau_private *dev_priv = dev->dev_private;
int channel, channel_old;
channel=NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1);
@@ -144,9 +144,9 @@ void nouveau_nv20_context_switch(drm_device_t *dev)
NV_WRITE(NV04_PGRAPH_FIFO,0x1);
}
-int nv20_graph_init(drm_device_t *dev) {
- drm_nouveau_private_t *dev_priv =
- (drm_nouveau_private_t *)dev->dev_private;
+int nv20_graph_init(struct drm_device *dev) {
+ struct drm_nouveau_private *dev_priv =
+ (struct drm_nouveau_private *)dev->dev_private;
uint32_t tmp, vramsz;
int ret, i;
@@ -240,7 +240,10 @@ int nv20_graph_init(drm_device_t *dev) {
return 0;
}
-void nv20_graph_takedown(drm_device_t *dev)
+void nv20_graph_takedown(struct drm_device *dev)
{
+ struct drm_nouveau_private *dev_priv = dev->dev_private;
+
+ nouveau_gpuobj_ref_del(dev, &dev_priv->ctx_table);
}