diff options
author | Jesse Barnes <jbarnes@jbarnes-mobile.amr.corp.intel.com> | 2007-09-24 14:41:46 -0700 |
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committer | Jesse Barnes <jbarnes@jbarnes-mobile.amr.corp.intel.com> | 2007-09-24 14:41:46 -0700 |
commit | 5cc3083179b19678456905a9122a3d0f04e6f623 (patch) | |
tree | 9b776bdd317aa5af68b7cbf8fabde12e20eccf8a /shared-core/nv04_timer.c | |
parent | 2a2d02bbc500140a861380df52ce66abcac39312 (diff) | |
parent | 54df1b9ff3b79097fedd8ed7bf54aca30a660cbd (diff) |
Merge branch 'master' into modesetting-101 - TTM & typedef removal
Conflicts:
linux-core/drmP.h
linux-core/drm_bo.c
linux-core/drm_drv.c
linux-core/drm_objects.h
shared-core/drm.h
shared-core/i915_dma.c
shared-core/i915_drv.h
shared-core/i915_irq.c
Mostly removing typedefs that snuck into the modesetting code and
updating to the latest TTM APIs. As of today, the i915 driver builds,
but there are likely to be problems, so debugging and bugfixes will
come next.
Diffstat (limited to 'shared-core/nv04_timer.c')
-rw-r--r-- | shared-core/nv04_timer.c | 27 |
1 files changed, 24 insertions, 3 deletions
diff --git a/shared-core/nv04_timer.c b/shared-core/nv04_timer.c index a4b4e826..08a27f4f 100644 --- a/shared-core/nv04_timer.c +++ b/shared-core/nv04_timer.c @@ -4,9 +4,9 @@ #include "nouveau_drm.h" int -nv04_timer_init(drm_device_t *dev) +nv04_timer_init(struct drm_device *dev) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; NV_WRITE(NV04_PTIMER_INTR_EN_0, 0x00000000); NV_WRITE(NV04_PTIMER_INTR_0, 0xFFFFFFFF); @@ -17,8 +17,29 @@ nv04_timer_init(drm_device_t *dev) return 0; } +uint64_t +nv04_timer_read(struct drm_device *dev) +{ + struct drm_nouveau_private *dev_priv = dev->dev_private; + uint32_t low; + /* From kmmio dumps on nv28 this looks like how the blob does this. + * It reads the high dword twice, before and after. + * The only explanation seems to be that the 64-bit timer counter + * advances between high and low dword reads and may corrupt the + * result. Not confirmed. + */ + uint32_t high2 = NV_READ(NV04_PTIMER_TIME_1); + uint32_t high1; + do { + high1 = high2; + low = NV_READ(NV04_PTIMER_TIME_0); + high2 = NV_READ(NV04_PTIMER_TIME_1); + } while(high1 != high2); + return (((uint64_t)high2) << 32) | (uint64_t)low; +} + void -nv04_timer_takedown(drm_device_t *dev) +nv04_timer_takedown(struct drm_device *dev) { } |