diff options
| author | Nian Wu <nian.wu@intel.com> | 2007-03-01 09:02:09 -0500 |
|---|---|---|
| committer | Nian Wu <nian@tinderbox.sh.intel.com> | 2007-03-01 09:02:09 -0500 |
| commit | 6c48b8e7ffd0af4d49855d7175e822f4af1f526f (patch) | |
| tree | 4ec7cf10147f3a17e6d4eeec8e48faa90880b8d9 /shared-core/nouveau_reg.h | |
| parent | 0bbbb46650667c84a50f1a675a7a910d6ef7df4b (diff) | |
| parent | 72caa48c82e4334d3292185dbadf758d2dd14c16 (diff) | |
Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline
Diffstat (limited to 'shared-core/nouveau_reg.h')
| -rw-r--r-- | shared-core/nouveau_reg.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/shared-core/nouveau_reg.h b/shared-core/nouveau_reg.h index 966600cf..95de558b 100644 --- a/shared-core/nouveau_reg.h +++ b/shared-core/nouveau_reg.h @@ -32,12 +32,20 @@ # define NV40_RAMHT_CONTEXT_ENGINE_SHIFT 20 # define NV40_RAMHT_CONTEXT_INSTANCE_SHIFT 0 +/* DMA object defines */ #define NV_DMA_ACCESS_RW 0 #define NV_DMA_ACCESS_RO 1 #define NV_DMA_ACCESS_WO 2 #define NV_DMA_TARGET_VIDMEM 0 +#define NV_DMA_TARGET_PCI 2 #define NV_DMA_TARGET_AGP 3 +/* Some object classes we care about in the drm */ +#define NV_CLASS_DMA_FROM_MEMORY 0x00000002 +#define NV_CLASS_DMA_TO_MEMORY 0x00000003 +#define NV_CLASS_NULL 0x00000030 +#define NV_CLASS_DMA_IN_MEMORY 0x0000003D + #define NV03_FIFO_SIZE 0x8000UL #define NV_MAX_FIFO_NUMBER 32 #define NV03_FIFO_REGS_SIZE 0x10000 |