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authorJesse Barnes <jbarnes@virtuousgeek.org>2008-08-07 17:15:50 -0700
committerJesse Barnes <jbarnes@virtuousgeek.org>2008-08-07 17:15:50 -0700
commit8074b2e83d18bbf85d1c3284f561d849c829dd4b (patch)
treee8f34c1779cb28336669296def5cad333b312914 /shared-core/i915_irq.c
parentc7fb19e9b074281f143b0e1c9d054ebcf5ff1091 (diff)
parent4585787bd1a1d782b9e7c06095f98d09165b8c23 (diff)
Make modesetting-gem build with recent kernels
Needed to merge in VM fault changes & pci_read_base API update.
Diffstat (limited to 'shared-core/i915_irq.c')
-rw-r--r--shared-core/i915_irq.c51
1 files changed, 49 insertions, 2 deletions
diff --git a/shared-core/i915_irq.c b/shared-core/i915_irq.c
index 00570e11..1b294bbd 100644
--- a/shared-core/i915_irq.c
+++ b/shared-core/i915_irq.c
@@ -1101,15 +1101,62 @@ int i915_vblank_swap(struct drm_device *dev, void *data,
*/
void i915_driver_irq_preinstall(struct drm_device * dev)
{
- return;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+ I915_WRITE16(HWSTAM, 0xeffe);
+ I915_WRITE16(IMR, 0x0);
+ I915_WRITE16(IER, 0x0);
}
int i915_driver_irq_postinstall(struct drm_device * dev)
{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ int ret, num_pipes = 2;
+
+ DRM_SPININIT(&dev_priv->swaps_lock, "swap");
+ INIT_LIST_HEAD(&dev_priv->vbl_swaps.head);
+ dev_priv->swaps_pending = 0;
+
+ DRM_SPININIT(&dev_priv->user_irq_lock, "userirq");
+ dev_priv->user_irq_refcount = 0;
+
+ ret = drm_vblank_init(dev, num_pipes);
+ if (ret)
+ return ret;
+
+ dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
+ dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
+
+ i915_enable_interrupt(dev);
+ DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);
+
+ /*
+ * Initialize the hardware status page IRQ location.
+ */
+
+ I915_WRITE(INSTPM, (1 << 5) | (1 << 21));
return 0;
}
void i915_driver_irq_uninstall(struct drm_device * dev)
{
- return;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ u32 temp;
+
+ if (!dev_priv)
+ return;
+
+ dev_priv->vblank_pipe = 0;
+
+ dev_priv->irq_enabled = 0;
+ I915_WRITE(HWSTAM, 0xffffffff);
+ I915_WRITE(IMR, 0xffffffff);
+ I915_WRITE(IER, 0x0);
+
+ temp = I915_READ(PIPEASTAT);
+ I915_WRITE(PIPEASTAT, temp);
+ temp = I915_READ(PIPEBSTAT);
+ I915_WRITE(PIPEBSTAT, temp);
+ temp = I915_READ(IIR);
+ I915_WRITE(IIR, temp);
}