diff options
| author | Eric Anholt <eric@anholt.net> | 2008-07-11 14:47:33 -0700 |
|---|---|---|
| committer | Eric Anholt <eric@anholt.net> | 2008-07-11 18:58:02 -0700 |
| commit | a0474be4e78d678eb615b37aad355effb955ee19 (patch) | |
| tree | 02105f9151e5dfa7ee0177656f3db2ea1c061513 /shared-core/i915_dma.c | |
| parent | 1f9a5307acfe2ef0d104f7036d2d93504dc7673f (diff) | |
intel-gem: Add two new ioctls for managing tiling on objects.
Various chips have exciting interactions between the CPU and the GPU's
different ways of accessing interleaved memory, so we need some kernel
assistance in determining how it works.
Only fully tested on GM965 so far.
Diffstat (limited to 'shared-core/i915_dma.c')
| -rw-r--r-- | shared-core/i915_dma.c | 10 |
1 files changed, 3 insertions, 7 deletions
diff --git a/shared-core/i915_dma.c b/shared-core/i915_dma.c index 6ee3d19f..c9a9d800 100644 --- a/shared-core/i915_dma.c +++ b/shared-core/i915_dma.c @@ -1068,13 +1068,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) ret = drm_addmap(dev, base, size, _DRM_REGISTERS, _DRM_KERNEL | _DRM_DRIVER, &dev_priv->mmio_map); - INIT_LIST_HEAD(&dev_priv->mm.active_list); - INIT_LIST_HEAD(&dev_priv->mm.flushing_list); - INIT_LIST_HEAD(&dev_priv->mm.inactive_list); - INIT_LIST_HEAD(&dev_priv->mm.request_list); - INIT_DELAYED_WORK(&dev_priv->mm.retire_work, - i915_gem_retire_work_handler); - dev_priv->mm.next_gem_seqno = 1; + i915_gem_load(dev); #ifdef __linux__ #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25) @@ -1217,6 +1211,8 @@ struct drm_ioctl_desc i915_ioctls[] = { DRM_IOCTL_DEF(DRM_I915_GEM_MMAP, i915_gem_mmap_ioctl, 0), DRM_IOCTL_DEF(DRM_I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, 0), DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, 0), + DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING, i915_gem_set_tiling, 0), + DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING, i915_gem_get_tiling, 0), }; int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls); |