re-tab and fixup the i915GM get core clock function to actually work

1 files changed, 91 insertions, 95 deletions

diff --git a/linux-core/intel_display.c b/linux-core/intel_display.c
index 92b39406..75d7359f 100644
--- a/linux-core/intel_display.c
+++ b/linux-core/intel_display.c
@@ -583,8 +583,9 @@ static int intel_get_core_clock_speed(drm_device_t *dev)
 	else if (IS_I945GM(dev) || IS_845G(dev))
 		return 200000;
 	else if (IS_I915GM(dev)) {
-#if 0
-		u16 gcfgc = pciReadWord(dev->PciTag, I915_GCFGC);
+		u16 gcfgc = 0;
+
+		pci_read_config_word(dev->pdev, I915_GCFGC, &gcfgc);
 		
 		if (gcfgc & I915_LOW_FREQUENCY_ENABLE)
 			return 133000;
@@ -597,7 +598,6 @@ static int intel_get_core_clock_speed(drm_device_t *dev)
 				return 190000;
 			}
 		}
-#endif
 	} else if (IS_I865G(dev))
 		return 266000;
 	else if (IS_I855(dev)) {
@@ -835,106 +835,102 @@ static void intel_crtc_mode_set(struct drm_crtc *crtc,
 	if (intel_panel_fitter_pipe(dev) == pipe)
 		I915_WRITE(PFIT_CONTROL, 0);
 
+	DRM_DEBUG("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
+	drm_mode_debug_printmodeline(dev, mode);
+	
 #if 0
-    xf86DrvMsg(pScrn->scrnIndex, X_INFO,
-	       "Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
-    xf86PrintModeline(pScrn->scrnIndex, mode);
-    if (!xf86ModesEqual(mode, adjusted_mode)) {
-	xf86DrvMsg(pScrn->scrnIndex, X_INFO,
-		   "Adjusted mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
-	xf86PrintModeline(pScrn->scrnIndex, mode);
-    }
-    i830PrintPll("chosen", &clock);
+	if (!xf86ModesEqual(mode, adjusted_mode)) {
+		xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+			   "Adjusted mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
+		xf86PrintModeline(pScrn->scrnIndex, mode);
+	}
+	i830PrintPll("chosen", &clock);
 #endif
 
-    if (dpll & DPLL_VCO_ENABLE)
-    {
+	if (dpll & DPLL_VCO_ENABLE) {
+		I915_WRITE(fp_reg, fp);
+		I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
+		I915_READ(dpll_reg);
+		udelay(150);
+	}
+	
+	/* The LVDS pin pair needs to be on before the DPLLs are enabled.
+	 * This is an exception to the general rule that mode_set doesn't turn
+	 * things on.
+	 */
+	if (is_lvds) {
+		u32 lvds = I915_READ(LVDS);
+		
+		lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | LVDS_PIPEB_SELECT;
+		/* Set the B0-B3 data pairs corresponding to whether we're going to
+		 * set the DPLLs for dual-channel mode or not.
+		 */
+		if (clock.p2 == 7)
+			lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
+		else
+			lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
+		
+		/* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
+		 * appropriately here, but we need to look more thoroughly into how
+		 * panels behave in the two modes.
+		 */
+		
+		I915_WRITE(LVDS, lvds);
+		I915_READ(LVDS);
+	}
+	
 	I915_WRITE(fp_reg, fp);
-	I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
+	I915_WRITE(dpll_reg, dpll);
 	I915_READ(dpll_reg);
+	/* Wait for the clocks to stabilize. */
 	udelay(150);
-    }
-
-    /* The LVDS pin pair needs to be on before the DPLLs are enabled.
-     * This is an exception to the general rule that mode_set doesn't turn
-     * things on.
-     */
-    if (is_lvds)
-    {
-	    u32 lvds = I915_READ(LVDS);
-
-	    lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | LVDS_PIPEB_SELECT;
-	    /* Set the B0-B3 data pairs corresponding to whether we're going to
-	     * set the DPLLs for dual-channel mode or not.
-	     */
-	    if (clock.p2 == 7)
-		    lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
-	    else
-		    lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
-	    
-	    /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
-	     * appropriately here, but we need to look more thoroughly into how
-	     * panels behave in the two modes.
-	     */
-	    
-	    I915_WRITE(LVDS, lvds);
-	    I915_READ(LVDS);
-    }
-    
-    I915_WRITE(fp_reg, fp);
-    I915_WRITE(dpll_reg, dpll);
-    I915_READ(dpll_reg);
-    /* Wait for the clocks to stabilize. */
-    udelay(150);
-    
-    if (IS_I965G(dev)) {
-	    int sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
-	    I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
-		       ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
-    } else {
-	    /* write it again -- the BIOS does, after all */
-	    I915_WRITE(dpll_reg, dpll);
-    }
-    I915_READ(dpll_reg);
-    /* Wait for the clocks to stabilize. */
-    udelay(150);
-    
-    I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
-	       ((adjusted_mode->crtc_htotal - 1) << 16));
-    I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
-	       ((adjusted_mode->crtc_hblank_end - 1) << 16));
-    I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
-	       ((adjusted_mode->crtc_hsync_end - 1) << 16));
-    I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
-	       ((adjusted_mode->crtc_vtotal - 1) << 16));
-    I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
-	       ((adjusted_mode->crtc_vblank_end - 1) << 16));
-    I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
-	       ((adjusted_mode->crtc_vsync_end - 1) << 16));
-    I915_WRITE(dspstride_reg, crtc->fb->pitch * (crtc->fb->bits_per_pixel / 8));
-    /* pipesrc and dspsize control the size that is scaled from, which should
-     * always be the user's requested size.
-     */
-    I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1));
-    I915_WRITE(dsppos_reg, 0);
-    I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
-    I915_WRITE(pipeconf_reg, pipeconf);
-    I915_READ(pipeconf_reg);
-
-    intel_wait_for_vblank(dev);
-
-    I915_WRITE(dspcntr_reg, dspcntr);
-
-    /* Flush the plane changes */
-    intel_pipe_set_base(crtc, x, y);
-
+	
+	if (IS_I965G(dev)) {
+		int sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
+		I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
+			   ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
+	} else {
+		/* write it again -- the BIOS does, after all */
+		I915_WRITE(dpll_reg, dpll);
+	}
+	I915_READ(dpll_reg);
+	/* Wait for the clocks to stabilize. */
+	udelay(150);
+	
+	I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
+		   ((adjusted_mode->crtc_htotal - 1) << 16));
+	I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
+		   ((adjusted_mode->crtc_hblank_end - 1) << 16));
+	I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
+		   ((adjusted_mode->crtc_hsync_end - 1) << 16));
+	I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
+		   ((adjusted_mode->crtc_vtotal - 1) << 16));
+	I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
+		   ((adjusted_mode->crtc_vblank_end - 1) << 16));
+	I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
+		   ((adjusted_mode->crtc_vsync_end - 1) << 16));
+	I915_WRITE(dspstride_reg, crtc->fb->pitch * (crtc->fb->bits_per_pixel / 8));
+	/* pipesrc and dspsize control the size that is scaled from, which should
+	 * always be the user's requested size.
+	 */
+	I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1));
+	I915_WRITE(dsppos_reg, 0);
+	I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
+	I915_WRITE(pipeconf_reg, pipeconf);
+	I915_READ(pipeconf_reg);
+	
+	intel_wait_for_vblank(dev);
+	
+	I915_WRITE(dspcntr_reg, dspcntr);
+	
+	/* Flush the plane changes */
+	intel_pipe_set_base(crtc, x, y);
+	
 #ifdef XF86DRI // TODO
 //   I830DRISetVBlankInterrupt (pScrn, TRUE);
 #endif
-
-    intel_wait_for_vblank(dev);    
-
-
+	
+	intel_wait_for_vblank(dev);    
 }
 
 /** Loads the palette/gamma unit for the CRTC with the prepared values */
@@ -1002,7 +998,7 @@ void intel_crtc_init(drm_device_t *dev, int pipe)
 	if (crtc == NULL)
 		return;
 
-	intel_crtc = kmalloc(sizeof(struct intel_crtc), GFP_KERNEL);
+	intel_crtc = kzalloc(sizeof(struct intel_crtc), GFP_KERNEL);
 	if (intel_crtc == NULL) {
 		kfree(crtc);
 		return;