radeon: remove unused legacy state

1 files changed, 0 insertions, 150 deletions

diff --git a/linux-core/radeon_mode.h b/linux-core/radeon_mode.h
index ee801604..7278c42b 100644
--- a/linux-core/radeon_mode.h
+++ b/linux-core/radeon_mode.h
@@ -161,160 +161,10 @@ struct radeon_pll {
 	uint32_t best_vco;
 };
 
-#define MAX_H_CODE_TIMING_LEN 32
-#define MAX_V_CODE_TIMING_LEN 32
-
-struct radeon_legacy_state {
-
-	uint32_t bus_cntl;
-
-	/* DAC */
-	uint32_t dac_cntl;
-	uint32_t dac2_cntl;
-	uint32_t dac_macro_cntl;
-
-	/* CRTC 1 */
-	uint32_t crtc_gen_cntl;
-	uint32_t crtc_ext_cntl;
-	uint32_t crtc_h_total_disp;
-	uint32_t crtc_h_sync_strt_wid;
-	uint32_t crtc_v_total_disp;
-	uint32_t crtc_v_sync_strt_wid;
-	uint32_t crtc_offset;
-	uint32_t crtc_offset_cntl;
-	uint32_t crtc_pitch;
-	uint32_t disp_merge_cntl;
-	uint32_t grph_buffer_cntl;
-	uint32_t crtc_more_cntl;
-	uint32_t crtc_tile_x0_y0;
-
-	/* CRTC 2 */
-	uint32_t crtc2_gen_cntl;
-	uint32_t crtc2_h_total_disp;
-	uint32_t crtc2_h_sync_strt_wid;
-	uint32_t crtc2_v_total_disp;
-	uint32_t crtc2_v_sync_strt_wid;
-	uint32_t crtc2_offset;
-	uint32_t crtc2_offset_cntl;
-	uint32_t crtc2_pitch;
-	uint32_t crtc2_tile_x0_y0;
-
-	uint32_t disp_output_cntl;
-	uint32_t disp_tv_out_cntl;
-	uint32_t disp_hw_debug;
-	uint32_t disp2_merge_cntl;
-	uint32_t grph2_buffer_cntl;
-
-	/* FP regs */
-	uint32_t fp_crtc_h_total_disp;
-	uint32_t fp_crtc_v_total_disp;
-	uint32_t fp_gen_cntl;
-	uint32_t fp2_gen_cntl;
-	uint32_t fp_h_sync_strt_wid;
-	uint32_t fp_h2_sync_strt_wid;
-	uint32_t fp_horz_stretch;
-	uint32_t fp_horz_vert_active;
-	uint32_t fp_panel_cntl;
-	uint32_t fp_v_sync_strt_wid;
-	uint32_t fp_v2_sync_strt_wid;
-	uint32_t fp_vert_stretch;
-	uint32_t lvds_gen_cntl;
-	uint32_t lvds_pll_cntl;
-	uint32_t tmds_pll_cntl;
-	uint32_t tmds_transmitter_cntl;
-
-	/* Computed values for PLL */
-	uint32_t dot_clock_freq;
-	uint32_t pll_output_freq;
-	int  feedback_div;
-	int  reference_div;
-	int  post_div;
-
-	/* PLL registers */
-	uint32_t ppll_ref_div;
-	uint32_t ppll_div_3;
-	uint32_t htotal_cntl;
-	uint32_t vclk_ecp_cntl;
-
-	/* Computed values for PLL2 */
-	uint32_t dot_clock_freq_2;
-	uint32_t pll_output_freq_2;
-	int feedback_div_2;
-	int reference_div_2;
-	int post_div_2;
-
-	/* PLL2 registers */
-	uint32_t p2pll_ref_div;
-	uint32_t p2pll_div_0;
-	uint32_t htotal_cntl2;
-	uint32_t pixclks_cntl;
-
-	bool palette_valid;
-	uint32_t palette[256];
-	uint32_t palette2[256];
-
-	uint32_t disp2_req_cntl1;
-	uint32_t disp2_req_cntl2;
-	uint32_t dmif_mem_cntl1;
-	uint32_t disp1_req_cntl1;
-
-	uint32_t fp_2nd_gen_cntl;
-	uint32_t fp2_2_gen_cntl;
-	uint32_t tmds2_cntl;
-	uint32_t tmds2_transmitter_cntl;
-
-	/* TV out registers */
-	uint32_t tv_master_cntl;
-	uint32_t tv_htotal;
-	uint32_t tv_hsize;
-	uint32_t tv_hdisp;
-	uint32_t tv_hstart;
-	uint32_t tv_vtotal;
-	uint32_t tv_vdisp;
-	uint32_t tv_timing_cntl;
-	uint32_t tv_vscaler_cntl1;
-	uint32_t tv_vscaler_cntl2;
-	uint32_t tv_sync_size;
-	uint32_t tv_vrestart;
-	uint32_t tv_hrestart;
-	uint32_t tv_frestart;
-	uint32_t tv_ftotal;
-	uint32_t tv_clock_sel_cntl;
-	uint32_t tv_clkout_cntl;
-	uint32_t tv_data_delay_a;
-	uint32_t tv_data_delay_b;
-	uint32_t tv_dac_cntl;
-	uint32_t tv_pll_cntl;
-	uint32_t tv_pll_cntl1;
-	uint32_t tv_pll_fine_cntl;
-	uint32_t tv_modulator_cntl1;
-	uint32_t tv_modulator_cntl2;
-	uint32_t tv_frame_lock_cntl;
-	uint32_t tv_pre_dac_mux_cntl;
-	uint32_t tv_rgb_cntl;
-	uint32_t tv_y_saw_tooth_cntl;
-	uint32_t tv_y_rise_cntl;
-	uint32_t tv_y_fall_cntl;
-	uint32_t tv_uv_adr;
-	uint32_t tv_upsamp_and_gain_cntl;
-	uint32_t tv_gain_limit_settings;
-	uint32_t tv_linear_gain_settings;
-	uint32_t tv_crc_cntl;
-	uint32_t tv_sync_cntl;
-	uint32_t gpiopad_a;
-	uint32_t pll_test_cntl;
-
-	uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN];
-	uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN];
-
-
-};
-
 struct radeon_mode_info {
 	struct atom_context *atom_context;
 	struct radeon_bios_connector bios_connector[RADEON_MAX_BIOS_CONNECTOR];
 	struct radeon_pll pll;
-	struct radeon_legacy_state legacy_state;
 };
 
 struct radeon_crtc {