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authorJesse Barnes <jbarnes@hobbes.virtuousgeek.org>2007-04-11 20:41:54 -0700
committerJesse Barnes <jbarnes@hobbes.virtuousgeek.org>2007-04-11 20:41:54 -0700
commite8bd9fdf31bf3db91431b69ce1fc8d419148c838 (patch)
tree6a71e0a919484e8a5255063d3abc691e05e70665 /linux-core/intel_display.c
parent0430a80fc7861a3397a3f2649dfeb9eff14359a5 (diff)
parentb1f0fd6dfbd1495aa08c6358e936582eeca042c8 (diff)
Merge branch 'modesetting-101' of git+ssh://git.freedesktop.org/git/mesa/drm into origin/modesetting-101
Diffstat (limited to 'linux-core/intel_display.c')
-rw-r--r--linux-core/intel_display.c21
1 files changed, 7 insertions, 14 deletions
diff --git a/linux-core/intel_display.c b/linux-core/intel_display.c
index 396f4cfa..aed86231 100644
--- a/linux-core/intel_display.c
+++ b/linux-core/intel_display.c
@@ -412,8 +412,7 @@ static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
case DPMSModeSuspend:
/* Enable the DPLL */
temp = I915_READ(dpll_reg);
- if ((temp & DPLL_VCO_ENABLE) == 0)
- {
+ if ((temp & DPLL_VCO_ENABLE) == 0) {
I915_WRITE(dpll_reg, temp);
I915_READ(dpll_reg);
/* Wait for the clocks to stabilize. */
@@ -435,8 +434,7 @@ static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
/* Enable the plane */
temp = I915_READ(dspcntr_reg);
- if ((temp & DISPLAY_PLANE_ENABLE) == 0)
- {
+ if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
/* Flush the plane changes */
I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
@@ -456,8 +454,7 @@ static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
/* Disable display plane */
temp = I915_READ(dspcntr_reg);
- if ((temp & DISPLAY_PLANE_ENABLE) != 0)
- {
+ if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
/* Flush the plane changes */
I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
@@ -719,11 +716,9 @@ static void intel_crtc_mode_set(struct drm_crtc *crtc,
dpll |= DPLLB_MODE_LVDS;
else
dpll |= DPLLB_MODE_DAC_SERIAL;
- if (is_sdvo)
- {
+ if (is_sdvo) {
dpll |= DPLL_DVO_HIGH_SPEED;
- if (IS_I945G(dev) || IS_I945GM(dev))
- {
+ if (IS_I945G(dev) || IS_I945GM(dev)) {
int sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
}
@@ -760,8 +755,7 @@ static void intel_crtc_mode_set(struct drm_crtc *crtc,
}
}
- if (is_tv)
- {
+ if (is_tv) {
/* XXX: just matching BIOS for now */
/* dpll |= PLL_REF_INPUT_TVCLKINBC; */
dpll |= 3;
@@ -801,8 +795,7 @@ static void intel_crtc_mode_set(struct drm_crtc *crtc,
dspcntr |= DISPPLANE_SEL_PIPE_B;
pipeconf = I915_READ(pipeconf_reg);
- if (pipe == 0 && !IS_I965G(dev))
- {
+ if (pipe == 0 && !IS_I965G(dev)) {
/* Enable pixel doubling when the dot clock is > 90% of the (display)
* core speed.
*