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authorEric Anholt <eric@anholt.net>2010-03-02 15:25:42 -0800
committerEric Anholt <eric@anholt.net>2010-03-02 15:39:37 -0800
commit292a5d73a244cec8f4d1042c6fec6618333c1e0e (patch)
tree35d088cc2d6127475b7ca64409a2403811814f53 /intel
parentacbaff24e071dce0d23c057c9890f3aec732b8ec (diff)
intel: Don't tile-align pitch for untiled buffers.
This allows Mesa to use drm_intel_bo_alloc_tiled() for its tiled buffers, since it makes its decision about pitch before telling libdrm. They happen to be the same choices for the tiled case.
Diffstat (limited to 'intel')
-rw-r--r--intel/intel_bufmgr_gem.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index 38e0ed9e..9cf4095b 100644
--- a/intel/intel_bufmgr_gem.c
+++ b/intel/intel_bufmgr_gem.c
@@ -258,7 +258,7 @@ drm_intel_gem_bo_tile_pitch(drm_intel_bufmgr_gem *bufmgr_gem,
unsigned long i;
if (tiling_mode == I915_TILING_NONE)
- return ROUND_UP_TO(pitch, tile_width);
+ return pitch;
/* 965 is flexible */
if (bufmgr_gem->gen >= 4)