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authorJesse Barnes <jbarnes@hobbes.virtuousgeek.org>2008-02-07 17:33:28 -0800
committerJesse Barnes <jbarnes@hobbes.virtuousgeek.org>2008-02-07 17:33:28 -0800
commitd63b57749f097b36df04c6beff9b35a1dd859523 (patch)
treeb797a885851b378873e816fc32c5091e8e21ea7a
parent6f19473191ae543fcc199d252c5865c0734d38ad (diff)
Restore pipeconf regs unconditionally
On many chipsets, the checks for DPLL enable or VGA mode will prevent the pipeconf regs from being restored, which could result in a blank display or X failing to come back after resume. So restore them unconditionally along with actually restoring pipe B's palette correctly.
-rw-r--r--linux-core/i915_drv.c11
1 files changed, 4 insertions, 7 deletions
diff --git a/linux-core/i915_drv.c b/linux-core/i915_drv.c
index c771ab3e..3e2bfc94 100644
--- a/linux-core/i915_drv.c
+++ b/linux-core/i915_drv.c
@@ -434,9 +434,7 @@ static int i915_resume(struct drm_device *dev)
I915_WRITE(DSPATILEOFF, dev_priv->saveDSPATILEOFF);
}
- if ((dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) &&
- (dev_priv->saveDPLL_A & DPLL_VGA_MODE_DIS))
- I915_WRITE(PIPEACONF, dev_priv->savePIPEACONF);
+ I915_WRITE(PIPEACONF, dev_priv->savePIPEACONF);
i915_restore_palette(dev, PIPE_A);
/* Enable the plane */
@@ -478,10 +476,9 @@ static int i915_resume(struct drm_device *dev)
I915_WRITE(DSPBTILEOFF, dev_priv->saveDSPBTILEOFF);
}
- if ((dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) &&
- (dev_priv->saveDPLL_B & DPLL_VGA_MODE_DIS))
- I915_WRITE(PIPEBCONF, dev_priv->savePIPEBCONF);
- i915_restore_palette(dev, PIPE_A);
+ I915_WRITE(PIPEBCONF, dev_priv->savePIPEBCONF);
+
+ i915_restore_palette(dev, PIPE_B);
/* Enable the plane */
I915_WRITE(DSPBCNTR, dev_priv->saveDSPBCNTR);
I915_WRITE(DSPBBASE, I915_READ(DSPBBASE));