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| author | Ben Skeggs <skeggsb@gmail.com> | 2009-02-11 10:48:36 +1000 |
|---|---|---|
| committer | Ben Skeggs <skeggsb@gmail.com> | 2009-02-11 11:22:41 +1000 |
| commit | bc92c0edf33f3f38275f6aa4e0639b3ddeef68ca (patch) | |
| tree | 7f8b95b6d8b3d220d14e7645d1e77130f1126380 | |
| parent | 7bbd605a21200e5e4beb94f261aefe30c4e7853d (diff) | |
drm/nv50: fix nv9x chipsets
NVIDIA do this fun little sequence after updating the PRAMIN page tables.
On 9xxx chips, none of the PRAMIN BAR bindings (except the initial one)
worked, hence the majority of the setup needed to create a channel
ended up in the wrong place, causing all sorts of fun.
This is done by NVIDIA on nv8x chips also, so we'll do it for them too,
even though they appear to work without it.
| -rw-r--r-- | shared-core/nv50_instmem.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/shared-core/nv50_instmem.c b/shared-core/nv50_instmem.c index b7a51f09..d76ebf38 100644 --- a/shared-core/nv50_instmem.c +++ b/shared-core/nv50_instmem.c @@ -297,6 +297,13 @@ nv50_instmem_bind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj) vram += NV50_INSTMEM_PAGE_SIZE; } + NV_WRITE(0x070000, 0x00000001); + while(NV_READ(0x070000) & 1); + NV_WRITE(0x100c80, 0x00040001); + while(NV_READ(0x100c80) & 1); + NV_WRITE(0x100c80, 0x00060001); + while(NV_READ(0x100c80) & 1); + gpuobj->im_bound = 1; return 0; } |