diff options
| author | Jesse Barnes <jbarnes@virtuousgeek.org> | 2012-03-18 16:51:18 -0500 |
|---|---|---|
| committer | Jesse Barnes <jbarnes@virtuousgeek.org> | 2012-09-13 11:50:59 -0700 |
| commit | 9d9cb8553c945fac15421770da233fb3e38396e0 (patch) | |
| tree | dd2408870901e28a7647f123713cce505f84c524 | |
| parent | 9c3c95fc0cb0945492279f0c7dcc0c2b1e8f463d (diff) | |
intel: add support for ValleyView
Just some PCI ID stuff to enable the right features.
| -rw-r--r-- | intel/intel_chipset.h | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h index b73fa0f9..a2eb8947 100644 --- a/intel/intel_chipset.h +++ b/intel/intel_chipset.h @@ -83,6 +83,8 @@ #define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D2A #define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D3A +#define PCI_CHIP_VALLEYVIEW_PO 0x0f30 /* power on board */ + #define IS_830(dev) (dev == 0x3577) #define IS_845(dev) (dev == 0x2562) #define IS_85X(dev) (dev == 0x3582) @@ -122,6 +124,8 @@ #define IS_I965GM(dev) (dev == 0x2A02) +#define IS_VALLEYVIEW(dev) (dev == 0xf30) + #define IS_GEN4(dev) (dev == 0x2972 || \ dev == 0x2982 || \ dev == 0x2992 || \ @@ -154,7 +158,8 @@ dev == PCI_CHIP_SANDYBRIDGE_S) #define IS_GEN7(devid) (IS_IVYBRIDGE(devid) || \ - IS_HASWELL(devid)) + IS_HASWELL(devid) || \ + IS_VALLEYVIEW(devid)) #define IS_IVYBRIDGE(dev) (dev == PCI_CHIP_IVYBRIDGE_GT1 || \ dev == PCI_CHIP_IVYBRIDGE_GT2 || \ |