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authorMaarten Maathuis <madman2003@gmail.com>2008-02-02 12:46:31 +0100
committerMaarten Maathuis <madman2003@gmail.com>2008-02-02 12:46:47 +0100
commit733e07663e50087ca1e9af8e9b5def556521e3b5 (patch)
tree020554b852f868e5fb8d10a068d0547ff1582bf8
parentc77b0937f290568604961fa0013691349c5fcf3b (diff)
nouveau: NV40 can/should now be able to run after the blob.
- Moved the fix from the ddx to drm, because it seemed more appropriate. - Don't be shy, report if it works for you or not.
-rw-r--r--shared-core/nouveau_reg.h1
-rw-r--r--shared-core/nv40_fb.c7
2 files changed, 8 insertions, 0 deletions
diff --git a/shared-core/nouveau_reg.h b/shared-core/nouveau_reg.h
index a2506146..283977b3 100644
--- a/shared-core/nouveau_reg.h
+++ b/shared-core/nouveau_reg.h
@@ -138,6 +138,7 @@
#define NV40_PFB_TLIMIT(i) (0x00100604 + (i*16))
#define NV40_PFB_TSIZE(i) (0x00100608 + (i*16))
#define NV40_PFB_TSTATUS(i) (0x0010060C + (i*16))
+#define NV40_PFB_UNK_800 0x00100800
#define NV04_PGRAPH_DEBUG_0 0x00400080
#define NV04_PGRAPH_DEBUG_1 0x00400084
diff --git a/shared-core/nv40_fb.c b/shared-core/nv40_fb.c
index ceae8079..ae784cb8 100644
--- a/shared-core/nv40_fb.c
+++ b/shared-core/nv40_fb.c
@@ -11,6 +11,13 @@ nv40_fb_init(struct drm_device *dev)
int num_tiles;
int i;
+ /* This is strictly a NV4x register (don't know about NV5x). */
+ /* The blob sets these to all kinds of values, and they mess up our setup. */
+ /* I got value 0x52802 instead. For some cards the blob even sets it back to 0x1. */
+ /* Note: the blob doesn't read this value, so i'm pretty sure this is safe for all cards. */
+ /* Any idea what this is? */
+ NV_WRITE(NV40_PFB_UNK_800, 0x1);
+
switch (dev_priv->chipset) {
case 0x40:
case 0x45: