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authorMaarten Maathuis <madman2003@gmail.com>2008-04-03 01:13:31 +0200
committerMaarten Maathuis <madman2003@gmail.com>2008-04-03 01:13:31 +0200
commit3fc444a5e8e35ffec7a1426c80c9644e5777ddbe (patch)
tree645207f8c73a08d0595010bfc491d06ff669cb0a
parent562f95ea96f08e1d73a872dc87237614292c873a (diff)
nv50: primitive display interrupt handler.
-rw-r--r--shared-core/nouveau_irq.c13
-rw-r--r--shared-core/nouveau_reg.h4
2 files changed, 17 insertions, 0 deletions
diff --git a/shared-core/nouveau_irq.c b/shared-core/nouveau_irq.c
index bceb81ab..ba3e1aa4 100644
--- a/shared-core/nouveau_irq.c
+++ b/shared-core/nouveau_irq.c
@@ -446,6 +446,14 @@ nouveau_crtc_irq_handler(struct drm_device *dev, int crtc)
}
}
+static void
+nouveau_nv50_display_irq_handler(struct drm_device *dev)
+{
+ struct drm_nouveau_private *dev_priv = dev->dev_private;
+
+ NV_WRITE(NV50_DISPLAY_SUPERVISOR, NV_READ(NV50_DISPLAY_SUPERVISOR));
+}
+
irqreturn_t
nouveau_irq_handler(DRM_IRQ_ARGS)
{
@@ -472,6 +480,11 @@ nouveau_irq_handler(DRM_IRQ_ARGS)
status &= ~NV_PMC_INTR_0_CRTCn_PENDING;
}
+ if (status & NV_PMC_INTR_0_NV50_DISPLAY_PENDING) {
+ nouveau_nv50_display_irq_handler(dev);
+ status &= ~NV_PMC_INTR_0_NV50_DISPLAY_PENDING;
+ }
+
if (status)
DRM_ERROR("Unhandled PMC INTR status bits 0x%08x\n", status);
diff --git a/shared-core/nouveau_reg.h b/shared-core/nouveau_reg.h
index 2f7d77cf..2594b9a7 100644
--- a/shared-core/nouveau_reg.h
+++ b/shared-core/nouveau_reg.h
@@ -87,6 +87,7 @@
# define NV_PMC_INTR_0_PGRAPH_PENDING (1<<12)
# define NV_PMC_INTR_0_CRTC0_PENDING (1<<24)
# define NV_PMC_INTR_0_CRTC1_PENDING (1<<25)
+# define NV_PMC_INTR_0_NV50_DISPLAY_PENDING (1<<26)
# define NV_PMC_INTR_0_CRTCn_PENDING (3<<24)
#define NV03_PMC_INTR_EN_0 0x00000140
# define NV_PMC_INTR_EN_0_MASTER_ENABLE (1<< 0)
@@ -535,6 +536,9 @@
#define NV_CRTC1_INTEN 0x00602140
# define NV_CRTC_INTR_VBLANK (1<<0)
+/* This name is a partial guess. */
+#define NV50_DISPLAY_SUPERVISOR 0x00610024
+
/* Fifo commands. These are not regs, neither masks */
#define NV03_FIFO_CMD_JUMP 0x20000000
#define NV03_FIFO_CMD_JUMP_OFFSET_MASK 0x1ffffffc