Mask off correct bits in M2REG_AUTO_LINK_STATUS for interrupt handling.

3 files changed, 64 insertions, 35 deletions

diff --git a/linux-core/xgi_cmdlist.h b/linux-core/xgi_cmdlist.h
index 07a2eb98..dc3fbe5a 100644
--- a/linux-core/xgi_cmdlist.h
+++ b/linux-core/xgi_cmdlist.h
@@ -27,35 +27,6 @@
 #ifndef _XGI_CMDLIST_H_
 #define _XGI_CMDLIST_H_
 
-#define		ONE_BIT_MASK							0x1
-#define		TWENTY_BIT_MASK							0xfffff
-#define 	M2REG_FLUSH_2D_ENGINE_MASK				(ONE_BIT_MASK<<20)
-#define 	M2REG_FLUSH_3D_ENGINE_MASK				TWENTY_BIT_MASK
-#define 	M2REG_FLUSH_FLIP_ENGINE_MASK			(ONE_BIT_MASK<<21)
-#define     BASE_3D_ENG                             0x2800
-#define     M2REG_AUTO_LINK_SETTING_ADDRESS         0x10
-#define 	M2REG_CLEAR_COUNTERS_MASK				(ONE_BIT_MASK<<4)
-#define 	M2REG_PCI_TRIGGER_MODE_MASK				(ONE_BIT_MASK<<1)
-#define 	BEGIN_VALID_MASK                        (ONE_BIT_MASK<<20)
-#define 	BEGIN_LINK_ENABLE_MASK                  (ONE_BIT_MASK<<31)
-#define 	BEGIN_BEGIN_IDENTIFICATION_MASK         (TWENTY_BIT_MASK<<0)
-#define     M2REG_PCI_TRIGGER_REGISTER_ADDRESS      0x14
-
-typedef enum {
-	FLUSH_2D = M2REG_FLUSH_2D_ENGINE_MASK,
-	FLUSH_3D = M2REG_FLUSH_3D_ENGINE_MASK,
-	FLUSH_FLIP = M2REG_FLUSH_FLIP_ENGINE_MASK
-} FLUSH_CODE;
-
-typedef enum {
-	AGPCMDLIST_SCRATCH_SIZE = 0x100,
-	AGPCMDLIST_BEGIN_SIZE = 0x004,
-	AGPCMDLIST_3D_SCRATCH_CMD_SIZE = 0x004,
-	AGPCMDLIST_2D_SCRATCH_CMD_SIZE = 0x00c,
-	AGPCMDLIST_FLUSH_CMD_LEN = 0x004,
-	AGPCMDLIST_DUMY_END_BATCH_LEN = AGPCMDLIST_BEGIN_SIZE
-} CMD_SIZE;
-
 struct xgi_cmdring_info {
 	/**
 	 * Kernel space pointer to the base of the command ring.
diff --git a/linux-core/xgi_drv.c b/linux-core/xgi_drv.c
index d0878184..f20df585 100644
--- a/linux-core/xgi_drv.c
+++ b/linux-core/xgi_drv.c
@@ -334,12 +334,19 @@ irqreturn_t xgi_kern_isr(DRM_IRQ_ARGS)
 {
 	struct drm_device *dev = (struct drm_device *) arg;
 	struct xgi_info *info = dev->dev_private;
-	const u32 irq_bits = DRM_READ32(info->mmio_map, 0x2810);
-
-
-	if ((irq_bits & 0x00000000) != 0) {
-		DRM_WRITE32(info->mmio_map, 0x2810,
-			    0x04000000 | irq_bits);
+	const u32 irq_bits = DRM_READ32(info->mmio_map,
+					(0x2800 
+					 + M2REG_AUTO_LINK_STATUS_ADDRESS))
+		& (M2REG_ACTIVE_TIMER_INTERRUPT_MASK
+		   | M2REG_ACTIVE_INTERRUPT_0_MASK
+		   | M2REG_ACTIVE_INTERRUPT_2_MASK
+		   | M2REG_ACTIVE_INTERRUPT_3_MASK);
+
+
+	if (irq_bits != 0) {
+		DRM_WRITE32(info->mmio_map, 
+			    0x2800 + M2REG_AUTO_LINK_SETTING_ADDRESS,
+			    M2REG_AUTO_LINK_SETTING_COMMAND | irq_bits);
 		return IRQ_HANDLED;
 	} else {
 		return IRQ_NONE;
diff --git a/linux-core/xgi_regs.h b/linux-core/xgi_regs.h
index b3a47f8e..57e93405 100644
--- a/linux-core/xgi_regs.h
+++ b/linux-core/xgi_regs.h
@@ -30,6 +30,57 @@
 #include "drmP.h"
 #include "drm.h"
 
+#define BASE_3D_ENG 0x2800
+
+#define MAKE_MASK(bits)  ((1U << (bits)) - 1)
+
+#define ONE_BIT_MASK        MAKE_MASK(1)
+#define TWENTY_BIT_MASK     MAKE_MASK(20)
+#define TWENTYONE_BIT_MASK  MAKE_MASK(21)
+#define TWENTYTWO_BIT_MASK  MAKE_MASK(22)
+
+#define M2REG_FLUSH_ENGINE_ADDRESS 0x000
+#define M2REG_FLUSH_ENGINE_COMMAND 0x00
+#define M2REG_FLUSH_FLIP_ENGINE_MASK              (ONE_BIT_MASK<<21)
+#define M2REG_FLUSH_2D_ENGINE_MASK                (ONE_BIT_MASK<<20)
+#define M2REG_FLUSH_3D_ENGINE_MASK                TWENTY_BIT_MASK
+
+/* Write register */
+#define M2REG_AUTO_LINK_SETTING_ADDRESS 0x010
+#define M2REG_AUTO_LINK_SETTING_COMMAND 0x04
+#define M2REG_CLEAR_TIMER_INTERRUPT_MASK          (ONE_BIT_MASK<<11)
+#define M2REG_CLEAR_INTERRUPT_3_MASK              (ONE_BIT_MASK<<10)
+#define M2REG_CLEAR_INTERRUPT_2_MASK              (ONE_BIT_MASK<<9)
+#define M2REG_CLEAR_INTERRUPT_0_MASK              (ONE_BIT_MASK<<8)
+#define M2REG_CLEAR_COUNTERS_MASK                 (ONE_BIT_MASK<<4)
+#define M2REG_PCI_TRIGGER_MODE_MASK               (ONE_BIT_MASK<<1)
+#define M2REG_INVALID_LIST_AUTO_INTERRUPT_MASK    (ONE_BIT_MASK<<0)
+
+/* Read register */
+#define M2REG_AUTO_LINK_STATUS_ADDRESS 0x010
+#define M2REG_AUTO_LINK_STATUS_COMMAND 0x04
+#define M2REG_ACTIVE_TIMER_INTERRUPT_MASK          (ONE_BIT_MASK<<11)
+#define M2REG_ACTIVE_INTERRUPT_3_MASK              (ONE_BIT_MASK<<10)
+#define M2REG_ACTIVE_INTERRUPT_2_MASK              (ONE_BIT_MASK<<9)
+#define M2REG_ACTIVE_INTERRUPT_0_MASK              (ONE_BIT_MASK<<8)
+#define M2REG_INVALID_LIST_AUTO_INTERRUPTED_MODE_MASK    (ONE_BIT_MASK<<0)
+
+#define     M2REG_PCI_TRIGGER_REGISTER_ADDRESS 0x014
+#define     M2REG_PCI_TRIGGER_REGISTER_COMMAND 0x05
+
+
+/**
+ * Begin instruction, double-word 0
+ */
+#define BEGIN_VALID_MASK                        (ONE_BIT_MASK<<20)
+#define BEGIN_BEGIN_IDENTIFICATION_MASK         TWENTY_BIT_MASK
+
+/**
+ * Begin instruction, double-word 1
+ */
+#define BEGIN_LINK_ENABLE_MASK                  (ONE_BIT_MASK<<31)
+#define BEGIN_COMMAND_LIST_LENGTH_MASK          TWENTYTWO_BIT_MASK
+
 
 /* Hardware access functions */
 static inline void OUT3C5B(struct drm_map * map, u8 index, u8 data)