nouveau: nv20 graph ctx switch.

Untested...

8 files changed, 194 insertions, 9 deletions

diff --git a/linux-core/Makefile.kernel b/linux-core/Makefile.kernel
index 1bfffa03..b531a70f 100644
--- a/linux-core/Makefile.kernel
+++ b/linux-core/Makefile.kernel
@@ -22,7 +22,8 @@ i830-objs   := i830_drv.o i830_dma.o i830_irq.o
 i915-objs   := i915_drv.o i915_dma.o i915_irq.o i915_mem.o i915_fence.o \
 		i915_buffer.o
 nouveau-objs := nouveau_drv.o nouveau_state.o nouveau_fifo.o nouveau_mem.o \
-		nouveau_object.o nouveau_irq.o nv10_graph.o nv30_graph.o nv40_graph.o
+		nouveau_object.o nouveau_irq.o nv10_graph.o nv30_graph.o nv40_graph.o \
+		nv20_graph.o
 radeon-objs := radeon_drv.o radeon_cp.o radeon_state.o radeon_mem.o radeon_irq.o r300_cmdbuf.o
 sis-objs    := sis_drv.o sis_mm.o
 ffb-objs    := ffb_drv.o ffb_context.o
diff --git a/linux-core/nv20_graph.c b/linux-core/nv20_graph.c
new file mode 120000
index 00000000..73049914
--- /dev/null
+++ b/linux-core/nv20_graph.c
@@ -0,0 +1 @@
+../shared-core/nv20_graph.c
\ No newline at end of file
diff --git a/shared-core/nouveau_drv.h b/shared-core/nouveau_drv.h
index 9466cdcd..4978c476 100644
--- a/shared-core/nouveau_drv.h
+++ b/shared-core/nouveau_drv.h
@@ -207,6 +207,11 @@ extern void nouveau_nv10_context_switch(drm_device_t *dev);
 extern int nv10_graph_init(drm_device_t *dev);
 extern int nv10_graph_context_create(drm_device_t *dev, int channel);
 
+/* nv20_graph.c */
+extern void nouveau_nv20_context_switch(drm_device_t *dev);
+extern int nv20_graph_init(drm_device_t *dev);
+extern int nv20_graph_context_create(drm_device_t *dev, int channel);
+
 /* nv30_graph.c */
 extern int nv30_graph_init(drm_device_t *dev);
 extern int nv30_graph_context_create(drm_device_t *dev, int channel);
diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c
index cb94afc5..1e2870f1 100644
--- a/shared-core/nouveau_fifo.c
+++ b/shared-core/nouveau_fifo.c
@@ -550,15 +550,22 @@ static int nouveau_fifo_alloc(drm_device_t* dev,drm_nouveau_fifo_alloc_t* init,
 	/* Construct inital RAMFC for new channel */
 	if (dev_priv->card_type < NV_10) {
 		nouveau_nv04_context_init(dev, init);
-	} else if (dev_priv->card_type < NV_30) {
+	} else if (dev_priv->card_type < NV_20) {
 		nv10_graph_context_create(dev, init->channel);
 		nouveau_nv10_context_init(dev, init);
-        } else if (dev_priv->card_type < NV_40) {
-                ret = nv30_graph_context_create(dev, init->channel);
-                if (ret) {
-                        nouveau_fifo_free(dev, init->channel);
-                        return ret;
-                }
+	} else if (dev_priv->card_type < NV_30) {
+		ret = nv20_graph_context_create(dev, init->channel);
+		if (ret) {
+			nouveau_fifo_free(dev, init->channel);
+			return ret;
+		}
+		nouveau_nv10_context_init(dev, init);
+	} else if (dev_priv->card_type < NV_40) {
+		ret = nv30_graph_context_create(dev, init->channel);
+		if (ret) {
+			nouveau_fifo_free(dev, init->channel);
+			return ret;
+		}
 		nouveau_nv30_context_init(dev, init);
 	} else {
 		ret = nv40_graph_context_create(dev, init->channel);
@@ -652,6 +659,13 @@ void nouveau_fifo_free(drm_device_t* dev,int n)
 
 	if (dev_priv->card_type >= NV_40)
 		nouveau_instmem_free(dev, dev_priv->fifos[n].ramin_grctx);
+	else if (dev_priv->card_type >= NV_30) {
+	}
+	else if (dev_priv->card_type >= NV_20) {
+		/* clear ctx table */
+		INSTANCE_WR(dev_priv->ctx_table, n, 0);
+		nouveau_instmem_free(dev, dev_priv->fifos[n].ramin_grctx);
+	}
 
 	/* reenable the fifo caches */
 	NV_WRITE(NV_PFIFO_CACHES, 0x00000001);
diff --git a/shared-core/nouveau_irq.c b/shared-core/nouveau_irq.c
index 638b094b..a92b8168 100644
--- a/shared-core/nouveau_irq.c
+++ b/shared-core/nouveau_irq.c
@@ -329,6 +329,9 @@ static void nouveau_pgraph_irq_handler(drm_device_t *dev)
 			case NV_10:
 				nouveau_nv10_context_switch(dev);
 				break;
+			case NV_20:
+				nouveau_nv20_context_switch(dev);
+				break;
 			default:
 				DRM_INFO("NV: Context switch not implemented\n");
 				break;
diff --git a/shared-core/nouveau_reg.h b/shared-core/nouveau_reg.h
index 8058e980..543be694 100644
--- a/shared-core/nouveau_reg.h
+++ b/shared-core/nouveau_reg.h
@@ -140,6 +140,8 @@
 #define NV_PGRAPH_FIFO                                     0x00400720
 
 #define NV_PGRAPH_BPIXEL                                   0x00400724
+#define NV_PGRAPH_RDI_INDEX                                0x00400750
+#define NV_PGRAPH_RDI_DATA                                 0x00400754
 #define NV_PGRAPH_FFINTFC_ST2                              0x00400764
 #define NV_PGRAPH_DMA_PITCH                                0x00400770
 #define NV_PGRAPH_DVD_COLORFMT                             0x00400774
diff --git a/shared-core/nouveau_state.c b/shared-core/nouveau_state.c
index 6448512c..f324c5ff 100644
--- a/shared-core/nouveau_state.c
+++ b/shared-core/nouveau_state.c
@@ -96,7 +96,11 @@ int nouveau_firstopen(struct drm_device *dev)
 	/* FIXME: doesn't belong here, and have no idea what it's for.. */
 	if (dev_priv->card_type >= NV_40)
 		nv40_graph_init(dev);
-	else if (dev_priv->card_type == NV_10)
+	else if (dev_priv->card_type >= NV_30) {
+	}
+	else if (dev_priv->card_type >= NV_20)
+		nv20_graph_init(dev);
+	else if (dev_priv->card_type >= NV_10)
 		nv10_graph_init(dev);
 
 	return 0;
diff --git a/shared-core/nv20_graph.c b/shared-core/nv20_graph.c
new file mode 100644
index 00000000..6d00effa
--- /dev/null
+++ b/shared-core/nv20_graph.c
@@ -0,0 +1,155 @@
+/* 
+ * Copyright 2007 Matthieu CASTET <castet.matthieu@free.fr>
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include "drmP.h"
+#include "drm.h"
+#include "nouveau_drv.h"
+#include "nouveau_drm.h"
+
+#define NV20_GRCTX_SIZE (3529)
+
+int nv20_graph_context_create(drm_device_t *dev, int channel) {
+	drm_nouveau_private_t *dev_priv =
+		(drm_nouveau_private_t *)dev->dev_private;
+	struct nouveau_fifo *chan = &dev_priv->fifos[channel];
+	unsigned int ctx_size = NV20_GRCTX_SIZE;
+	int i;
+
+	/* Alloc and clear RAMIN to store the context */
+	chan->ramin_grctx = nouveau_instmem_alloc(dev, ctx_size, 4);
+	if (!chan->ramin_grctx)
+		return DRM_ERR(ENOMEM);
+	for (i=0; i<ctx_size; i+=4)
+		INSTANCE_WR(chan->ramin_grctx, i/4, 0x00000000);
+
+	/* Initialise default context values */
+	INSTANCE_WR(chan->ramin_grctx, 10, channel << 24); /* CTX_USER */
+
+	INSTANCE_WR(dev_priv->ctx_table, channel, nouveau_chip_instance_get(dev, chan->ramin_grctx));
+
+	return 0;
+}
+
+static void nv20_graph_rdi(drm_device_t *dev) {
+	drm_nouveau_private_t *dev_priv =
+		(drm_nouveau_private_t *)dev->dev_private;
+	int i;
+
+	NV_WRITE(NV_PGRAPH_RDI_INDEX, 0x2c80000);
+	for (i = 0; i < 32; i++)
+		NV_WRITE(NV_PGRAPH_RDI_DATA, 0);
+
+	nouveau_wait_for_idle(dev);
+}
+
+/* Save current context (from PGRAPH) into the channel's context
+ */
+static void nv20_graph_context_save_current(drm_device_t *dev, int channel) {
+	drm_nouveau_private_t *dev_priv =
+		(drm_nouveau_private_t *)dev->dev_private;
+	uint32_t instance;
+
+	instance = INSTANCE_RD(dev_priv->ctx_table, channel);
+	if (!instance) {
+		return;
+	}
+	if (instance != nouveau_chip_instance_get(dev, dev_priv->fifos[channel].ramin_grctx))
+		DRM_ERROR("nv20_graph_context_save_current : bad instance\n");
+
+	NV_WRITE(NV_PGRAPH_CHANNEL_CTX_SIZE, instance);
+	NV_WRITE(NV_PGRAPH_CHANNEL_CTX_POINTER, 2 /* save ctx */);
+}
+
+
+/* Restore the context for a specific channel into PGRAPH
+ */
+static void nv20_graph_context_restore(drm_device_t *dev, int channel) {
+	drm_nouveau_private_t *dev_priv =
+		(drm_nouveau_private_t *)dev->dev_private;
+	uint32_t instance;
+
+	instance = INSTANCE_RD(dev_priv->ctx_table, channel);
+	if (!instance) {
+		return;
+	}
+	if (instance != nouveau_chip_instance_get(dev, dev_priv->fifos[channel].ramin_grctx))
+		DRM_ERROR("nv20_graph_context_restore_current : bad instance\n");
+
+	NV_WRITE(NV_PGRAPH_CTX_USER, channel << 24);
+	NV_WRITE(NV_PGRAPH_CHANNEL_CTX_SIZE, instance);
+	NV_WRITE(NV_PGRAPH_CHANNEL_CTX_POINTER, 1 /* restore ctx */);
+}
+
+void nouveau_nv20_context_switch(drm_device_t *dev)
+{
+	drm_nouveau_private_t *dev_priv = dev->dev_private;
+	int channel, channel_old;
+
+	channel=NV_READ(NV_PFIFO_CACH1_PSH1)&(nouveau_fifo_number(dev)-1);
+	channel_old = (NV_READ(NV_PGRAPH_CTX_USER) >> 24) & (nouveau_fifo_number(dev)-1);
+
+	DRM_INFO("NV: PGRAPH context switch interrupt channel %x -> %x\n",channel_old, channel);
+
+	NV_WRITE(NV_PGRAPH_FIFO,0x0);
+
+	nv20_graph_context_save_current(dev, channel_old);
+	
+	nouveau_wait_for_idle(dev);
+
+	NV_WRITE(NV_PGRAPH_CTX_CONTROL, 0x10000000);
+
+	nv20_graph_context_restore(dev, channel_old);
+
+	nouveau_wait_for_idle(dev);
+	
+	if ((NV_READ(NV_PGRAPH_CTX_USER) >> 24) != channel)
+		DRM_ERROR("nouveau_nv20_context_switch : wrong channel restored %x %x!!!\n", channel, NV_READ(NV_PGRAPH_CTX_USER) >> 24);
+
+	NV_WRITE(NV_PGRAPH_CTX_CONTROL, 0x10010100);
+	NV_WRITE(NV_PGRAPH_FFINTFC_ST2, NV_READ(NV_PGRAPH_FFINTFC_ST2)&0xCFFFFFFF);
+
+	NV_WRITE(NV_PGRAPH_FIFO,0x1);
+}
+
+int nv20_graph_init(drm_device_t *dev) {
+	drm_nouveau_private_t *dev_priv =
+		(drm_nouveau_private_t *)dev->dev_private;
+	int i;
+
+	/* Create Context Pointer Table */
+	dev_priv->ctx_table_size = 32 * 4;
+	dev_priv->ctx_table = nouveau_instmem_alloc(dev, dev_priv->ctx_table_size, 4);
+	if (!dev_priv->ctx_table)
+		return DRM_ERR(ENOMEM);
+
+	for (i=0; i< dev_priv->ctx_table_size; i+=4)
+		INSTANCE_WR(dev_priv->ctx_table, i/4, 0x00000000);
+
+	NV_WRITE(NV_PGRAPH_CHANNEL_CTX_TABLE, nouveau_chip_instance_get(dev, dev_priv->ctx_table));
+
+	//XXX need to be done and save/restore for each fifo ???
+	nv20_graph_rdi(dev);
+
+	return 0;
+}