radeon: add initial support for legacy crtc/encoders.

not all there yet

9 files changed, 1454 insertions, 163 deletions

diff --git a/linux-core/Makefile.kernel b/linux-core/Makefile.kernel
index b15a12ab..576de5b2 100644
--- a/linux-core/Makefile.kernel
+++ b/linux-core/Makefile.kernel
@@ -41,7 +41,7 @@ nouveau-objs := nouveau_drv.o nouveau_state.o nouveau_fifo.o nouveau_mem.o \
 		nv50_fbcon.o
 radeon-objs := radeon_drv.o radeon_cp.o radeon_state.o radeon_mem.o radeon_irq.o r300_cmdbuf.o radeon_gem.o \
 	 radeon_buffer.o radeon_fence.o atom.o radeon_display.o radeon_atombios.o radeon_i2c.o radeon_connectors.o radeon_cs.o \
-	atombios_crtc.o radeon_encoders.o radeon_fb.o radeon_combios.o
+	atombios_crtc.o radeon_encoders.o radeon_fb.o radeon_combios.o radeon_legacy_crtc.o radeon_legacy_encoders.o
 sis-objs    := sis_drv.o sis_mm.o
 ffb-objs    := ffb_drv.o ffb_context.o
 savage-objs := savage_drv.o savage_bci.o savage_state.o
diff --git a/linux-core/radeon_combios.c b/linux-core/radeon_combios.c
index e2b768ca..8a1dd8b3 100644
--- a/linux-core/radeon_combios.c
+++ b/linux-core/radeon_combios.c
@@ -175,6 +175,45 @@ bool radeon_combios_get_lvds_info(struct radeon_encoder *encoder)
 	return true;
 }
 
+bool radeon_combios_get_tmds_info(struct radeon_encoder *encoder)
+{
+	struct drm_device *dev = encoder->base.dev;
+	struct drm_radeon_private *dev_priv = dev->dev_private;
+	uint16_t tmp;
+	int i, n;
+	uint8_t ver;
+
+	tmp = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x34);
+	if (!tmp) {
+		DRM_INFO("No TMDS info found in BIOS\n");
+		return false;
+	}
+
+	ver = radeon_bios8(dev_priv, tmp);
+	DRM_INFO("DFP table revision: %d\n", ver);
+	if (ver == 3) {
+		n = radeon_bios8(dev_priv, tmp + 5) + 1;
+		if (n > 4) n = 4;
+		for (i = 0; i < n; i++) {
+			encoder->tmds_pll[i].value = radeon_bios32(dev_priv, tmp+i*10+0x08);
+			encoder->tmds_pll[i].freq = radeon_bios16(dev_priv, tmp+i*10+0x10);	
+		}
+		return true;
+	} else if (ver == 4) {
+		int stride = 0;
+		n = radeon_bios8(dev_priv, tmp + 5) + 1;
+		if (n > 4) n = 4;
+		for (i = 0; i < n; i++) {
+			encoder->tmds_pll[i].value = radeon_bios32(dev_priv, tmp+stride+0x08);
+			encoder->tmds_pll[i].freq = radeon_bios16(dev_priv, tmp+stride+0x10);
+			if (i == 0) stride += 10;
+			else stride += 6;
+		}
+		return true;
+	}
+	return false;
+}
+
 static void radeon_apply_legacy_quirks(struct drm_device *dev, int bios_index)
 {
 	struct drm_radeon_private *dev_priv = dev->dev_private;
diff --git a/linux-core/radeon_display.c b/linux-core/radeon_display.c
index 7a7b5856..1e5233d2 100644
--- a/linux-core/radeon_display.c
+++ b/linux-core/radeon_display.c
@@ -116,38 +116,7 @@ void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
 	radeon_crtc->lut_b[regno] = blue >> 8;
 }
 
-void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
-{
-}
-
-
 
-static bool radeon_crtc_mode_fixup(struct drm_crtc *crtc,
-				   struct drm_display_mode *mode,
-				   struct drm_display_mode *adjusted_mode)
-{
-	return true;
-}
-
-static void radeon_crtc_mode_set(struct drm_crtc *crtc,
-				 struct drm_display_mode *mode,
-				 struct drm_display_mode *adjusted_mode,
-				 int x, int y)
-{
-
-}
-
-void radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y)
-{
-}
-
-static void radeon_crtc_prepare(struct drm_crtc *crtc)
-{
-}
-
-static void radeon_crtc_commit(struct drm_crtc *crtc)
-{
-}
 
 static void avivo_lock_cursor(struct drm_crtc *crtc, bool lock)
 {
@@ -263,15 +232,6 @@ static void radeon_crtc_destroy(struct drm_crtc *crtc)
 	kfree(radeon_crtc);
 }
 
-static const struct drm_crtc_helper_funcs radeon_helper_funcs = {
-	.dpms = radeon_crtc_dpms,
-	.mode_fixup = radeon_crtc_mode_fixup,
-	.mode_set = radeon_crtc_mode_set,
-	.mode_set_base = radeon_crtc_set_base,
-	.prepare = radeon_crtc_prepare,
-	.commit = radeon_crtc_commit,
-};
-
 static const struct drm_crtc_funcs radeon_crtc_funcs = {
 	.cursor_set = radeon_crtc_cursor_set,
 	.cursor_move = radeon_crtc_cursor_move,
@@ -309,7 +269,7 @@ static void radeon_crtc_init(struct drm_device *dev, int index)
 	if (dev_priv->is_atom_bios && dev_priv->chip_family > CHIP_RS690)
 		radeon_atombios_init_crtc(dev, radeon_crtc);
 	else
-		drm_crtc_helper_add(&radeon_crtc->base, &radeon_helper_funcs);
+		radeon_legacy_init_crtc(dev, radeon_crtc);
 }
 
 bool radeon_legacy_setup_enc_conn(struct drm_device *dev)
@@ -360,8 +320,14 @@ bool radeon_setup_enc_conn(struct drm_device *dev)
 		if ((mode_info->bios_connector[i].connector_type == CONNECTOR_DVI_I) ||
 		    (mode_info->bios_connector[i].connector_type == CONNECTOR_DVI_A) ||
 		    (mode_info->bios_connector[i].connector_type == CONNECTOR_VGA)) {
-			if (radeon_is_avivo(dev_priv))
+			if (radeon_is_avivo(dev_priv)) {
 				encoder = radeon_encoder_atom_dac_add(dev, i, mode_info->bios_connector[i].dac_type, 0);
+			} else {
+				if (mode_info->bios_connector[i].dac_type == DAC_PRIMARY)
+					encoder = radeon_encoder_legacy_primary_dac_add(dev, i, 0);
+//				else if (mode_info->bios_connector[i].dac_type == DAC_TVDAC)
+//					encoder radeon_encoder_legacy_secondary_dac_add(dev, i, 0);
+			}
 			if (encoder)
 				drm_mode_connector_attach_encoder(connector, encoder);
 		}
@@ -371,6 +337,10 @@ bool radeon_setup_enc_conn(struct drm_device *dev)
 		    (mode_info->bios_connector[i].connector_type == CONNECTOR_DVI_D)) {
 			if (radeon_is_avivo(dev_priv))
 				encoder = radeon_encoder_atom_tmds_add(dev, i, mode_info->bios_connector[i].dac_type);
+			else {
+				if (mode_info->bios_connector[i].tmds_type == TMDS_INT)
+					encoder = radeon_encoder_legacy_tmds_int_add(dev, i);
+			}
 			if (encoder)
 				drm_mode_connector_attach_encoder(connector, encoder);
 		}
diff --git a/linux-core/radeon_encoders.c b/linux-core/radeon_encoders.c
index 1b75bd6a..9a2d63ea 100644
--- a/linux-core/radeon_encoders.c
+++ b/linux-core/radeon_encoders.c
@@ -30,9 +30,9 @@
 
 extern int atom_debug;
 
-static void radeon_rmx_mode_fixup(struct drm_encoder *encoder,
-				  struct drm_display_mode *mode,
-				  struct drm_display_mode *adjusted_mode)
+void radeon_rmx_mode_fixup(struct drm_encoder *encoder,
+			   struct drm_display_mode *mode,
+			   struct drm_display_mode *adjusted_mode)
 {
 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 	if (mode->hdisplay < radeon_encoder->panel_xres ||
@@ -319,7 +319,7 @@ static const struct drm_encoder_helper_funcs radeon_atom_lvtma_helper_funcs = {
 	.commit = radeon_lvtma_commit,
 };
 
-static void radeon_enc_destroy(struct drm_encoder *encoder)
+void radeon_enc_destroy(struct drm_encoder *encoder)
 {
 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 	drm_encoder_cleanup(encoder);
@@ -895,68 +895,3 @@ struct drm_encoder *radeon_encoder_atom_tmds_add(struct drm_device *dev, int bio
 	return encoder;
 }
 
-static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode)
-{
-	struct drm_device *dev = encoder->dev;
-}
-
-static void radeon_legacy_lvds_prepare(struct drm_encoder *encoder)
-{
-	radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_OFF);
-}
-
-static void radeon_legacy_lvds_commit(struct drm_encoder *encoder)
-{
-	radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_ON);
-}
-
-static void radeon_legacy_lvds_mode_set(struct drm_encoder *encoder,
-				  struct drm_display_mode *mode,
-				  struct drm_display_mode *adjusted_mode)
-{
-
-
-}
-
-static const struct drm_encoder_helper_funcs radeon_legacy_lvds_helper_funcs = {
-	.dpms = radeon_legacy_lvds_dpms,
-	.mode_fixup = radeon_lvtma_mode_fixup,
-	.prepare = radeon_legacy_lvds_prepare,
-	.mode_set = radeon_legacy_lvds_mode_set,
-	.commit = radeon_legacy_lvds_commit,
-};
-
-
-static const struct drm_encoder_funcs radeon_legacy_lvds_enc_funcs = {
-	.destroy = radeon_enc_destroy,
-};
-
-struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index)
-{
-	struct drm_radeon_private *dev_priv = dev->dev_private;
-	struct radeon_mode_info *mode_info = &dev_priv->mode_info;
-	struct radeon_encoder *radeon_encoder;
-	struct drm_encoder *encoder;
-	radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
-	if (!radeon_encoder) {
-		return NULL;
-	}
-
-	encoder = &radeon_encoder->base;
-
-	encoder->possible_crtcs = 0x3;
-	encoder->possible_clones = 0;
-	drm_encoder_init(dev, encoder, &radeon_legacy_lvds_enc_funcs,
-			 DRM_MODE_ENCODER_LVDS);
-
-	drm_encoder_helper_add(encoder, &radeon_legacy_lvds_helper_funcs);
-
-	/* TODO get the LVDS info from the BIOS for panel size etc. */
-	/* get the lvds info from the bios */
-	radeon_combios_get_lvds_info(radeon_encoder);
-
-	/* LVDS gets default RMX full scaling */
-	radeon_encoder->rmx_type = RMX_FULL;
-
-	return encoder;
-}
diff --git a/linux-core/radeon_legacy_crtc.c b/linux-core/radeon_legacy_crtc.c
new file mode 100644
index 00000000..eb005a07
--- /dev/null
+++ b/linux-core/radeon_legacy_crtc.c
@@ -0,0 +1,748 @@
+/*
+ * Copyright 2007-8 Advanced Micro Devices, Inc.
+ * Copyright 2008 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Dave Airlie
+ *          Alex Deucher
+ */
+#include "drmP.h"
+#include "radeon_drm.h"
+#include "radeon_drv.h"
+
+#include "drm_crtc_helper.h"
+
+void radeon_restore_common_regs(struct drm_device *dev, struct radeon_legacy_state *state)
+{
+	/* don't need this yet */
+}
+
+void radeon_restore_crtc_registers(struct drm_device *dev, struct radeon_legacy_state *state)
+{
+	struct drm_radeon_private *dev_priv = dev->dev_private;
+
+	RADEON_WRITE(RADEON_CRTC_GEN_CNTL, state->crtc_gen_cntl |
+		     RADEON_CRTC_DISP_REQ_EN_B);
+
+	RADEON_WRITE_P(RADEON_CRTC_EXT_CNTL, state->crtc_ext_cntl,
+		       RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | RADEON_CRTC_DISPLAY_DIS);
+
+	RADEON_WRITE(RADEON_CRTC_H_TOTAL_DISP, state->crtc_h_total_disp);
+	RADEON_WRITE(RADEON_CRTC_H_SYNC_STRT_WID, state->crtc_h_sync_strt_wid);
+	RADEON_WRITE(RADEON_CRTC_V_TOTAL_DISP, state->crtc_v_total_disp);
+	RADEON_WRITE(RADEON_CRTC_V_SYNC_STRT_WID, state->crtc_v_sync_strt_wid);
+
+	if (radeon_is_r300(dev_priv))
+		RADEON_WRITE(R300_CRTC_TILE_X0_Y0, state->crtc_tile_x0_y0);
+
+	RADEON_WRITE(RADEON_CRTC_OFFSET_CNTL, state->crtc_offset_cntl);
+	RADEON_WRITE(RADEON_CRTC_OFFSET, state->crtc_offset);
+
+	RADEON_WRITE(RADEON_CRTC_PITCH, state->crtc_pitch);
+	RADEON_WRITE(RADEON_DISP_MERGE_CNTL, state->disp_merge_cntl);
+
+	/* if dell server */
+	if (0)
+	{
+		RADEON_WRITE(RADEON_TV_DAC_CNTL, state->tv_dac_cntl);
+		RADEON_WRITE(RADEON_DISP_HW_DEBUG, state->disp_hw_debug);
+		RADEON_WRITE(RADEON_DAC_CNTL2, state->dac2_cntl);
+		RADEON_WRITE(RADEON_CRTC2_GEN_CNTL, state->crtc2_gen_cntl);
+	}
+
+	RADEON_WRITE(RADEON_CRTC_GEN_CNTL, state->crtc_gen_cntl);
+}
+
+void radeon_restore_crtc2_registers(struct drm_device *dev, struct radeon_legacy_state *state)
+{
+	struct drm_radeon_private *dev_priv = dev->dev_private;
+
+	/* We prevent the CRTC from hitting th
+  e memory controller until
+	 * fully programmed
+	 */
+	RADEON_WRITE(RADEON_CRTC2_GEN_CNTL,
+	       state->crtc2_gen_cntl | RADEON_CRTC2_VSYNC_DIS |
+	       RADEON_CRTC2_HSYNC_DIS | RADEON_CRTC2_DISP_DIS |
+	       RADEON_CRTC2_DISP_REQ_EN_B);
+
+	RADEON_WRITE(RADEON_CRTC2_H_TOTAL_DISP,    state->crtc2_h_total_disp);
+	RADEON_WRITE(RADEON_CRTC2_H_SYNC_STRT_WID, state->crtc2_h_sync_strt_wid);
+	RADEON_WRITE(RADEON_CRTC2_V_TOTAL_DISP,    state->crtc2_v_total_disp);
+	RADEON_WRITE(RADEON_CRTC2_V_SYNC_STRT_WID, state->crtc2_v_sync_strt_wid);
+	
+	RADEON_WRITE(RADEON_FP_H2_SYNC_STRT_WID,   state->fp_h2_sync_strt_wid);
+	RADEON_WRITE(RADEON_FP_V2_SYNC_STRT_WID,   state->fp_v2_sync_strt_wid);
+
+	if (radeon_is_r300(dev_priv))
+		RADEON_WRITE(R300_CRTC2_TILE_X0_Y0, state->crtc2_tile_x0_y0);
+	RADEON_WRITE(RADEON_CRTC2_OFFSET_CNTL,     state->crtc2_offset_cntl);
+	RADEON_WRITE(RADEON_CRTC2_OFFSET,          state->crtc2_offset);
+
+	RADEON_WRITE(RADEON_CRTC2_PITCH,           state->crtc2_pitch);
+	RADEON_WRITE(RADEON_DISP2_MERGE_CNTL,      state->disp2_merge_cntl);
+
+	RADEON_WRITE(RADEON_CRTC2_GEN_CNTL, state->crtc2_gen_cntl);
+}
+
+static void radeon_pll_wait_for_read_update_complete(struct drm_device *dev)
+{
+	struct drm_radeon_private *dev_priv = dev->dev_private;
+	int i = 0;
+
+	/* FIXME: Certain revisions of R300 can't recover here.  Not sure of
+	   the cause yet, but this workaround will mask the problem for now.
+	   Other chips usually will pass at the very first test, so the
+	   workaround shouldn't have any effect on them. */
+	for (i = 0;
+	     (i < 10000 &&
+	      RADEON_READ_PLL(dev_priv, RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
+	     i++);
+}
+
+static void radeon_pll_write_update(struct drm_device *dev)
+{
+	struct drm_radeon_private *dev_priv = dev->dev_private;
+
+	while (RADEON_READ_PLL(dev_priv, RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
+
+	RADEON_WRITE_PLL_P(dev_priv, RADEON_PPLL_REF_DIV,
+			   RADEON_PPLL_ATOMIC_UPDATE_W,
+			   ~(RADEON_PPLL_ATOMIC_UPDATE_W));
+}
+
+static void radeon_pll2_wait_for_read_update_complete(struct drm_device *dev)
+{
+	struct drm_radeon_private *dev_priv = dev->dev_private;
+	int i = 0;
+
+
+	/* FIXME: Certain revisions of R300 can't recover here.  Not sure of
+	   the cause yet, but this workaround will mask the problem for now.
+	   Other chips usually will pass at the very first test, so the
+	   workaround shouldn't have any effect on them. */
+	for (i = 0;
+	     (i < 10000 &&
+	      RADEON_READ_PLL(dev_priv, RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
+	     i++);
+}
+
+static void radeon_pll2_write_update(struct drm_device *dev)
+{
+	struct drm_radeon_private *dev_priv = dev->dev_private;
+
+	while (RADEON_READ_PLL(dev_priv, RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
+	
+	RADEON_WRITE_PLL_P(dev_priv, RADEON_P2PLL_REF_DIV,
+			   RADEON_P2PLL_ATOMIC_UPDATE_W,
+			   ~(RADEON_P2PLL_ATOMIC_UPDATE_W));
+}
+
+static uint8_t radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div,
+				       uint16_t fb_div)
+{
+	unsigned int vcoFreq;
+
+        if (!ref_div)
+		return 1;
+
+	vcoFreq = ((unsigned)ref_freq & fb_div) / ref_div;
+
+	/*
+	 * This is horribly crude: the VCO frequency range is divided into
+	 * 3 parts, each part having a fixed PLL gain value.
+	 */
+	if (vcoFreq >= 30000)
+		/*
+		 * [300..max] MHz : 7
+		 */
+		return 7;
+	else if (vcoFreq >= 18000)
+		/*
+		 * [180..300) MHz : 4
+		 */
+		return 4;
+	else
+		/*
+		 * [0..180) MHz : 1
+		 */
+		return 1;
+}
+
+void radeon_restore_pll_registers(struct drm_device *dev, struct radeon_legacy_state *state)
+{
+	struct drm_radeon_private *dev_priv = dev->dev_private;
+	uint8_t pll_gain;
+	
+	pll_gain = radeon_compute_pll_gain(dev_priv->mode_info.pll.reference_freq,
+					  state->ppll_ref_div & RADEON_PPLL_REF_DIV_MASK,
+					  state->ppll_div_3 & RADEON_PPLL_FB3_DIV_MASK);
+
+	if (dev_priv->flags & RADEON_IS_MOBILITY) {
+		/* A temporal workaround for the occational blanking on certain laptop panels.
+		   This appears to related to the PLL divider registers (fail to lock?).
+		   It occurs even when all dividers are the same with their old settings.
+		   In this case we really don't need to fiddle with PLL registers.
+		   By doing this we can avoid the blanking problem with some panels.
+		*/
+		if ((state->ppll_ref_div == (RADEON_READ_PLL(dev_priv, RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) &&
+		    (state->ppll_div_3 == (RADEON_READ_PLL(dev_priv, RADEON_PPLL_DIV_3) & 
+					   (RADEON_PPLL_POST3_DIV_MASK | RADEON_PPLL_FB3_DIV_MASK)))) {
+			RADEON_WRITE_P(RADEON_CLOCK_CNTL_INDEX,
+				       RADEON_PLL_DIV_SEL,
+				       ~(RADEON_PLL_DIV_SEL));
+			radeon_pll_errata_after_index(dev_priv);
+			return;
+		}
+	}
+	
+	RADEON_WRITE_PLL_P(dev_priv, RADEON_VCLK_ECP_CNTL,
+		RADEON_VCLK_SRC_SEL_CPUCLK,
+		~(RADEON_VCLK_SRC_SEL_MASK));
+
+	RADEON_WRITE_PLL_P(dev_priv,
+		RADEON_PPLL_CNTL,
+		RADEON_PPLL_RESET
+		| RADEON_PPLL_ATOMIC_UPDATE_EN
+		| RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
+		| ((uint32_t)pll_gain << RADEON_PPLL_PVG_SHIFT),
+		~(RADEON_PPLL_RESET
+		  | RADEON_PPLL_ATOMIC_UPDATE_EN
+		  | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
+		  | RADEON_PPLL_PVG_MASK));
+
+	RADEON_WRITE_P(RADEON_CLOCK_CNTL_INDEX,
+		RADEON_PLL_DIV_SEL,
+		~(RADEON_PLL_DIV_SEL));
+	radeon_pll_errata_after_index(dev_priv);
+
+	if (radeon_is_r300(dev_priv) ||
+	    (dev_priv->chip_family == CHIP_RS300) ||
+	    (dev_priv->chip_family == CHIP_RS400) ||
+	    (dev_priv->chip_family == CHIP_RS480)) {
+		if (state->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
+			/* When restoring console mode, use saved PPLL_REF_DIV
+			 * setting.
+			 */
+			RADEON_WRITE_PLL_P(dev_priv, RADEON_PPLL_REF_DIV,
+				state->ppll_ref_div,
+				0);
+		} else {
+			/* R300 uses ref_div_acc field as real ref divider */
+			RADEON_WRITE_PLL_P(dev_priv, RADEON_PPLL_REF_DIV,
+				(state->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
+				~R300_PPLL_REF_DIV_ACC_MASK);
+		}
+	} else {
+		RADEON_WRITE_PLL_P(dev_priv, RADEON_PPLL_REF_DIV,
+			state->ppll_ref_div,
+			~RADEON_PPLL_REF_DIV_MASK);
+	}
+
+	RADEON_WRITE_PLL_P(dev_priv, RADEON_PPLL_DIV_3,
+		state->ppll_div_3,
+		~RADEON_PPLL_FB3_DIV_MASK);
+
+	RADEON_WRITE_PLL_P(dev_priv, RADEON_PPLL_DIV_3,
+		state->ppll_div_3,
+		~RADEON_PPLL_POST3_DIV_MASK);
+
+	radeon_pll_write_update(dev);
+	radeon_pll_wait_for_read_update_complete(dev);
+
+	RADEON_WRITE_PLL(dev_priv, RADEON_HTOTAL_CNTL, state->htotal_cntl);
+
+	RADEON_WRITE_PLL_P(dev_priv, RADEON_PPLL_CNTL,
+		0,
+		~(RADEON_PPLL_RESET
+		  | RADEON_PPLL_SLEEP
+		  | RADEON_PPLL_ATOMIC_UPDATE_EN
+		  | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN));
+
+	DRM_DEBUG("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
+		  state->ppll_ref_div,
+		  state->ppll_div_3,
+		  (unsigned)state->htotal_cntl,
+		  RADEON_READ_PLL(dev_priv, RADEON_PPLL_CNTL));
+	DRM_DEBUG("Wrote: rd=%d, fd=%d, pd=%d\n",
+		  state->ppll_ref_div & RADEON_PPLL_REF_DIV_MASK,
+		  state->ppll_div_3 & RADEON_PPLL_FB3_DIV_MASK,
+		  (state->ppll_div_3 & RADEON_PPLL_POST3_DIV_MASK) >> 16);
+
+	mdelay(50); /* Let the clock to lock */
+
+	RADEON_WRITE_PLL_P(dev_priv, RADEON_VCLK_ECP_CNTL,
+			   RADEON_VCLK_SRC_SEL_PPLLCLK,
+			   ~(RADEON_VCLK_SRC_SEL_MASK));
+
+	/*RADEON_WRITE_PLL(dev_priv, RADEON_VCLK_ECP_CNTL, state->vclk_ecp_cntl);*/
+
+}
+
+void radeon_restore_pll2_registers(struct drm_device *dev, struct radeon_legacy_state *state)
+{
+	struct drm_radeon_private *dev_priv = dev->dev_private;
+	uint8_t pll_gain;
+
+	pll_gain = radeon_compute_pll_gain(dev_priv->mode_info.pll.reference_freq,
+					   state->p2pll_ref_div & RADEON_P2PLL_REF_DIV_MASK,
+					   state->p2pll_div_0 & RADEON_P2PLL_FB0_DIV_MASK);
+
+
+	RADEON_WRITE_PLL_P(dev_priv, RADEON_PIXCLKS_CNTL,
+		RADEON_PIX2CLK_SRC_SEL_CPUCLK,
+		~(RADEON_PIX2CLK_SRC_SEL_MASK));
+
+	RADEON_WRITE_PLL_P(dev_priv,
+		RADEON_P2PLL_CNTL,
+		RADEON_P2PLL_RESET
+		| RADEON_P2PLL_ATOMIC_UPDATE_EN
+		| ((uint32_t)pll_gain << RADEON_P2PLL_PVG_SHIFT),
+		~(RADEON_P2PLL_RESET
+		  | RADEON_P2PLL_ATOMIC_UPDATE_EN
+		  | RADEON_P2PLL_PVG_MASK));
+
+
+	RADEON_WRITE_PLL_P(dev_priv, RADEON_P2PLL_REF_DIV,
+		state->p2pll_ref_div,
+		~RADEON_P2PLL_REF_DIV_MASK);
+
+	RADEON_WRITE_PLL_P(dev_priv, RADEON_P2PLL_DIV_0,
+		state->p2pll_div_0,
+		~RADEON_P2PLL_FB0_DIV_MASK);
+
+	RADEON_WRITE_PLL_P(dev_priv, RADEON_P2PLL_DIV_0,
+		state->p2pll_div_0,
+		~RADEON_P2PLL_POST0_DIV_MASK);
+
+	radeon_pll2_write_update(dev);
+	radeon_pll2_wait_for_read_update_complete(dev);
+
+	RADEON_WRITE_PLL(dev_priv, RADEON_HTOTAL2_CNTL, state->htotal_cntl2);
+
+	RADEON_WRITE_PLL_P(dev_priv, RADEON_P2PLL_CNTL,
+		0,
+		~(RADEON_P2PLL_RESET
+		  | RADEON_P2PLL_SLEEP
+		  | RADEON_P2PLL_ATOMIC_UPDATE_EN));
+
+	DRM_DEBUG("Wrote2: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
+		  (unsigned)state->p2pll_ref_div,
+		  (unsigned)state->p2pll_div_0,
+		  (unsigned)state->htotal_cntl2,
+		  RADEON_READ_PLL(dev_priv, RADEON_P2PLL_CNTL));
+	DRM_DEBUG("Wrote2: rd=%u, fd=%u, pd=%u\n",
+		  (unsigned)state->p2pll_ref_div & RADEON_P2PLL_REF_DIV_MASK,
+		  (unsigned)state->p2pll_div_0 & RADEON_P2PLL_FB0_DIV_MASK,
+		  (unsigned)((state->p2pll_div_0 &
+			      RADEON_P2PLL_POST0_DIV_MASK) >>16));
+
+	mdelay(50); /* Let the clock to lock */
+
+	RADEON_WRITE_PLL_P(dev_priv, RADEON_PIXCLKS_CNTL,
+		RADEON_PIX2CLK_SRC_SEL_P2PLLCLK,
+		~(RADEON_PIX2CLK_SRC_SEL_MASK));
+
+	RADEON_WRITE_PLL(dev_priv, RADEON_PIXCLKS_CNTL, state->pixclks_cntl);
+
+
+}
+
+
+void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
+{
+	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
+	struct drm_device *dev = crtc->dev;
+	struct drm_radeon_private *dev_priv = dev->dev_private;
+
+	uint32_t mask;
+
+	mask = radeon_crtc->crtc_id ? 
+		(RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_VSYNC_DIS | RADEON_CRTC2_HSYNC_DIS | RADEON_CRTC2_DISP_REQ_EN_B) :
+		(RADEON_CRTC_DISPLAY_DIS | RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS);
+
+	switch(mode) {
+	case DRM_MODE_DPMS_ON:
+		if (radeon_crtc->crtc_id) {
+			RADEON_WRITE_P(RADEON_CRTC2_GEN_CNTL, 0, ~mask);
+		} else {
+			RADEON_WRITE_P(RADEON_CRTC_GEN_CNTL, 0, ~RADEON_CRTC_DISP_REQ_EN_B);
+			RADEON_WRITE_P(RADEON_CRTC_EXT_CNTL, 0, ~mask);
+		}
+		break;
+	case DRM_MODE_DPMS_STANDBY:
+		if (radeon_crtc->crtc_id) {
+			RADEON_WRITE_P(RADEON_CRTC2_GEN_CNTL, (RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_HSYNC_DIS), ~mask);
+		} else {
+			RADEON_WRITE_P(RADEON_CRTC_GEN_CNTL, 0, ~RADEON_CRTC_DISP_REQ_EN_B);
+			RADEON_WRITE_P(RADEON_CRTC_EXT_CNTL, (RADEON_CRTC_DISPLAY_DIS | RADEON_CRTC_HSYNC_DIS), ~mask);
+		}
+		break;
+	case DRM_MODE_DPMS_SUSPEND:
+		if (radeon_crtc->crtc_id) {
+			RADEON_WRITE_P(RADEON_CRTC2_GEN_CNTL, (RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_VSYNC_DIS), ~mask);
+		} else {
+			RADEON_WRITE_P(RADEON_CRTC_GEN_CNTL, 0, ~RADEON_CRTC_DISP_REQ_EN_B);
+			RADEON_WRITE_P(RADEON_CRTC_EXT_CNTL, (RADEON_CRTC_DISPLAY_DIS | RADEON_CRTC_VSYNC_DIS), ~mask);
+		}
+		break;
+	case DRM_MODE_DPMS_OFF:
+		if (radeon_crtc->crtc_id) {
+			RADEON_WRITE_P(RADEON_CRTC2_GEN_CNTL, mask, ~mask);
+		} else {
+			RADEON_WRITE_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~RADEON_CRTC_DISP_REQ_EN_B);
+			RADEON_WRITE_P(RADEON_CRTC_EXT_CNTL, mask, ~mask);
+		}
+		break;
+	}
+  
+	if (mode != DRM_MODE_DPMS_OFF) {
+		radeon_crtc_load_lut(crtc);
+	}
+}
+
+static bool radeon_init_crtc_base(struct drm_crtc *crtc, struct radeon_legacy_state *state, int x, int y)
+{
+	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);	
+	struct drm_device *dev = crtc->dev;
+	struct drm_radeon_private *dev_priv = dev->dev_private;
+	struct radeon_framebuffer *radeon_fb;
+	struct drm_radeon_gem_object *obj_priv;
+	uint32_t base;
+
+	radeon_fb = to_radeon_framebuffer(crtc->fb);
+
+	obj_priv = radeon_fb->obj->driver_private;
+
+	state->crtc_offset = obj_priv->bo->offset + dev_priv->fb_location;
+
+	state->crtc_offset_cntl = 0;
+
+	/* TODO tiling */
+	if (0) {
+		if (radeon_is_r300(dev_priv)) {
+			state->crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN |
+						   R300_CRTC_MICRO_TILE_BUFFER_DIS |
+						   R300_CRTC_MACRO_TILE_EN);
+		} else {
+			state->crtc_offset_cntl |= RADEON_CRTC_TILE_EN;
+		}
+	} else {
+		if (radeon_is_r300(dev_priv)) {
+			state->crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN |
+						    R300_CRTC_MICRO_TILE_BUFFER_DIS |
+						    R300_CRTC_MACRO_TILE_EN);
+		} else {
+			state->crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN;
+		}
+	}
+
+	base = obj_priv->bo->offset;
+
+	/* TODO more tiling */
+	if (0) {
+		if (radeon_is_r300(dev_priv)) {
+			    state->crtc_tile_x0_y0 = x | (y << 16);
+			    base &= ~0x7ff;
+		    } else {
+			    int byteshift = crtc->fb->bits_per_pixel >> 4;
+			    int tile_addr = (((y >> 3) * crtc->fb->width + x) >> (8 - byteshift)) << 11;
+			    base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8);
+			    state->crtc_offset_cntl |= (y % 16);
+		    }
+	} else {
+		int offset = y * crtc->fb->pitch + x;
+		switch (crtc->fb->bits_per_pixel) {
+		}
+		base += offset;
+	}
+
+	base &= ~7;
+
+	/* update sarea TODO */
+
+	state->crtc_offset = base;
+	return true;
+}
+
+static bool radeon_init_crtc_registers(struct drm_crtc *crtc, struct radeon_legacy_state *state,
+				      struct drm_display_mode *mode)
+{
+	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);	
+	struct drm_device *dev = crtc->dev;
+	struct drm_radeon_private *dev_priv = dev->dev_private;
+	int format;
+	int hsync_start;
+	int hsync_wid;
+	int vsync_wid;
+
+	switch (crtc->fb->depth) {
+		
+	case 15: format = 3; break;      /*  555 */
+	case 16: format = 4; break;      /*  565 */
+	case 24: format = 5; break;      /*  RGB */
+	case 32: format = 6; break;      /* xRGB */
+	default:
+		return false;
+	}
+
+	state->crtc_gen_cntl = (RADEON_CRTC_EXT_DISP_EN
+				| RADEON_CRTC_EN
+				| (format << 8)
+				| ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
+				   ? RADEON_CRTC_DBL_SCAN_EN
+				   : 0)
+				| ((mode->flags & DRM_MODE_FLAG_CSYNC)
+				   ? RADEON_CRTC_CSYNC_EN
+				   : 0)
+				| ((mode->flags & DRM_MODE_FLAG_INTERLACE)
+				   ? RADEON_CRTC_INTERLACE_EN
+				   : 0));
+
+	state->crtc_ext_cntl |= (RADEON_XCRT_CNT_EN|
+				 RADEON_CRTC_VSYNC_DIS |
+				 RADEON_CRTC_HSYNC_DIS |
+				 RADEON_CRTC_DISPLAY_DIS);
+
+	state->disp_merge_cntl = RADEON_READ(RADEON_DISP_MERGE_CNTL);
+	state->disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
+
+	state->crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
+				   | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff)
+				      << 16));
+
+	hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
+	if (!hsync_wid)       hsync_wid = 1;
+	hsync_start = mode->crtc_hsync_start - 8;
+
+	state->crtc_h_sync_strt_wid = ((hsync_start & 0x1fff)
+				      | ((hsync_wid & 0x3f) << 16)
+				      | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
+					 ? RADEON_CRTC_H_SYNC_POL
+					 : 0));
+
+	/* This works for double scan mode. */
+	state->crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
+				   | ((mode->crtc_vdisplay - 1) << 16));
+
+	vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
+	if (!vsync_wid)       vsync_wid = 1;
+
+	state->crtc_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
+				      | ((vsync_wid & 0x1f) << 16)
+				      | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
+					 ? RADEON_CRTC_V_SYNC_POL
+					 : 0));
+
+	state->crtc_pitch  = (((crtc->fb->pitch * crtc->fb->bits_per_pixel) +
+			      ((crtc->fb->bits_per_pixel * 8) -1)) /
+			     (crtc->fb->bits_per_pixel * 8));
+	state->crtc_pitch |= state->crtc_pitch << 16;
+
+	/* TODO -> Dell Server */
+	if (0) {
+//		state->dac2_cntl = info->StatedReg->dac2_cntl;
+//		state->tv_dac_cntl = info->StatedReg->tv_dac_cntl;
+//		state->crtc2_gen_cntl = info->StatedReg->crtc2_gen_cntl;
+//		state->disp_hw_debug = info->StatedReg->disp_hw_debug;
+
+//		state->dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
+//		state->dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
+
+		/* For CRT on DAC2, don't turn it on if BIOS didn't
+		   enable it, even it's detected.
+		*/
+		state->disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
+		state->tv_dac_cntl &= ~((1<<2) | (3<<8) | (7<<24) | (0xff<<16));
+		state->tv_dac_cntl |= (0x03 | (2<<8) | (0x58<<16));
+	}
+
+	return true;
+}
+
+static void radeon_init_pll_registers(struct drm_crtc *crtc, struct radeon_legacy_state *state,
+				      struct drm_display_mode *mode, int flags)
+{
+	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);	
+	struct drm_device *dev = crtc->dev;
+	struct drm_radeon_private *dev_priv = dev->dev_private;
+	uint32_t feedback_div = 0;
+	uint32_t reference_div = 0;
+	uint32_t post_divider = 0;
+	uint32_t freq = 0;
+	struct radeon_pll *pll = &dev_priv->mode_info.pll;
+	struct {
+		int divider;
+		int bitvalue;
+	} *post_div, post_divs[]   = {
+		/* From RAGE 128 VR/RAGE 128 GL Register
+		 * Reference Manual (Technical Reference
+		 * Manual P/N RRG-G04100-C Rev. 0.04), page
+		 * 3-17 (PLL_DIV_[3:0]).
+		 */
+		{  1, 0 },              /* VCLK_SRC                 */
+		{  2, 1 },              /* VCLK_SRC/2               */
+		{  4, 2 },              /* VCLK_SRC/4               */
+		{  8, 3 },              /* VCLK_SRC/8               */
+		{  3, 4 },              /* VCLK_SRC/3               */
+		{ 16, 5 },              /* VCLK_SRC/16              */
+		{  6, 6 },              /* VCLK_SRC/6               */
+		{ 12, 7 },              /* VCLK_SRC/12              */
+		{  0, 0 }
+	};
+	
+#if 0 // TODO
+	if ((flags & RADEON_PLL_USE_BIOS_DIVS) && info->UseBiosDividers) {
+		state->ppll_ref_div = info->RefDivider;
+		state->ppll_div_3   = info->FeedbackDivider | (info->PostDivider << 16);
+		state->htotal_cntl  = 0;
+		return;
+	}
+#endif
+
+	DRM_DEBUG("\n");
+	radeon_compute_pll(pll, mode->clock, &freq, &feedback_div, &reference_div, &post_divider, flags);
+
+	for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
+		if (post_div->divider == post_divider)
+			break;
+	}
+
+	if (!post_div->divider) {
+		state->pll_output_freq = freq;
+		post_div = &post_divs[0];
+	}
+	
+	state->dot_clock_freq = freq;
+	state->feedback_div   = feedback_div;
+	state->reference_div  = reference_div;
+	state->post_div       = post_divider;
+
+	DRM_DEBUG("dc=%u, of=%u, fd=%d, rd=%d, pd=%d\n",
+		  (unsigned)state->dot_clock_freq,
+		  (unsigned)state->pll_output_freq,
+		  state->feedback_div,
+		  state->reference_div,
+		  state->post_div);
+
+	state->ppll_ref_div   = state->reference_div;
+
+#if defined(__powerpc__) && (0) /* TODO */
+	/* apparently programming this otherwise causes a hang??? */
+	if (info->MacModel == RADEON_MAC_IBOOK)
+		state->ppll_div_3 = 0x000600ad;
+	else
+#endif
+		state->ppll_div_3     = (state->feedback_div | (post_div->bitvalue << 16));
+	
+    state->htotal_cntl    = mode->htotal & 0x7;
+
+    state->vclk_ecp_cntl = (RADEON_READ_PLL(dev_priv, RADEON_VCLK_ECP_CNTL) &
+			    ~RADEON_VCLK_SRC_SEL_MASK) | RADEON_VCLK_SRC_SEL_PPLLCLK;
+
+}
+
+static bool radeon_crtc_mode_fixup(struct drm_crtc *crtc,
+				   struct drm_display_mode *mode,
+				   struct drm_display_mode *adjusted_mode)
+{
+	return true;
+}
+
+static void radeon_crtc_mode_set(struct drm_crtc *crtc,
+				 struct drm_display_mode *mode,
+				 struct drm_display_mode *adjusted_mode,
+				 int x, int y)
+{
+	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);	
+	struct drm_device *dev = crtc->dev;
+	struct drm_radeon_private *dev_priv = dev->dev_private;
+	struct drm_encoder *encoder;
+	int pll_flags = RADEON_PLL_LEGACY | RADEON_PLL_PREFER_LOW_REF_DIV;
+	int i;
+
+	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
+		struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+
+		if (encoder->crtc == crtc) {
+			if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
+				pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;
+			if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS)
+				pll_flags |= RADEON_PLL_USE_BIOS_DIVS | RADEON_PLL_USE_REF_DIV;
+		}
+	}
+
+	switch(radeon_crtc->crtc_id) {
+	case 0:
+		radeon_init_crtc_registers(crtc, &dev_priv->mode_info.legacy_state, adjusted_mode);
+		radeon_init_crtc_base(crtc, &dev_priv->mode_info.legacy_state, crtc->x, crtc->y);
+//		dot_clock = adjusted_mode->clock / 1000;
+
+		//	if (dot_clock)
+		radeon_init_pll_registers(crtc, &dev_priv->mode_info.legacy_state, adjusted_mode,
+					  pll_flags);
+		break;
+	case 1:
+		break;
+
+	}
+
+	/* TODO TV */
+
+	switch (radeon_crtc->crtc_id) {
+	case 0:
+		radeon_restore_crtc_registers(dev, &dev_priv->mode_info.legacy_state);
+		radeon_restore_pll_registers(dev, &dev_priv->mode_info.legacy_state);
+		break;
+	case 1:
+		radeon_restore_crtc2_registers(dev, &dev_priv->mode_info.legacy_state);
+		radeon_restore_pll2_registers(dev, &dev_priv->mode_info.legacy_state);
+		break;
+	}
+
+}
+
+void radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y)
+{
+}
+
+static void radeon_crtc_prepare(struct drm_crtc *crtc)
+{
+}
+
+static void radeon_crtc_commit(struct drm_crtc *crtc)
+{
+}
+
+static const struct drm_crtc_helper_funcs legacy_helper_funcs = {
+	.dpms = radeon_crtc_dpms,
+	.mode_fixup = radeon_crtc_mode_fixup,
+	.mode_set = radeon_crtc_mode_set,
+	.mode_set_base = radeon_crtc_set_base,
+	.prepare = radeon_crtc_prepare,
+	.commit = radeon_crtc_commit,
+};
+
+
+void radeon_legacy_init_crtc(struct drm_device *dev,
+			       struct radeon_crtc *radeon_crtc)
+{
+	drm_crtc_helper_add(&radeon_crtc->base, &legacy_helper_funcs);
+}
diff --git a/linux-core/radeon_legacy_encoders.c b/linux-core/radeon_legacy_encoders.c
new file mode 100644
index 00000000..8846653d
--- /dev/null
+++ b/linux-core/radeon_legacy_encoders.c
@@ -0,0 +1,391 @@
+/*
+ * Copyright 2007-8 Advanced Micro Devices, Inc.
+ * Copyright 2008 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Dave Airlie
+ *          Alex Deucher
+ */
+#include "drmP.h"
+#include "drm_crtc_helper.h"
+#include "radeon_drm.h"
+#include "radeon_drv.h"
+
+
+void radeon_restore_dac_registers(struct drm_device *dev, struct radeon_legacy_state *state)
+{
+	struct drm_radeon_private *dev_priv = dev->dev_private;
+
+	if (radeon_is_r300(dev_priv))
+		RADEON_WRITE_P(RADEON_GPIOPAD_A, state->gpiopad_a, ~1);
+
+	RADEON_WRITE_P(RADEON_DAC_CNTL,
+		       state->dac_cntl,
+		       RADEON_DAC_RANGE_CNTL |
+		       RADEON_DAC_BLANKING);
+
+	RADEON_WRITE(RADEON_DAC_CNTL2, state->dac2_cntl);
+
+	if ((dev_priv->chip_family != CHIP_R100) &&
+	    (dev_priv->chip_family != CHIP_R200))
+		RADEON_WRITE (RADEON_TV_DAC_CNTL, state->tv_dac_cntl);
+
+	RADEON_WRITE(RADEON_DISP_OUTPUT_CNTL, state->disp_output_cntl);
+	
+	if ((dev_priv->chip_family == CHIP_R200) ||
+	    radeon_is_r300(dev_priv)) {
+		RADEON_WRITE(RADEON_DISP_TV_OUT_CNTL, state->disp_tv_out_cntl);
+	} else {
+		RADEON_WRITE(RADEON_DISP_HW_DEBUG, state->disp_hw_debug);
+	}
+
+	RADEON_WRITE(RADEON_DAC_MACRO_CNTL, state->dac_macro_cntl);
+
+	/* R200 DAC connected via DVO */
+	if (dev_priv->chip_family == CHIP_R200)
+		RADEON_WRITE(RADEON_FP2_GEN_CNTL, state->fp2_gen_cntl);
+}
+
+
+/* Write TMDS registers */
+void radeon_restore_fp_registers(struct drm_device *dev, struct radeon_legacy_state *state)
+{
+	struct drm_radeon_private *dev_priv = dev->dev_private;
+
+	RADEON_WRITE(RADEON_TMDS_PLL_CNTL,        state->tmds_pll_cntl);
+	RADEON_WRITE(RADEON_TMDS_TRANSMITTER_CNTL,state->tmds_transmitter_cntl);
+	RADEON_WRITE(RADEON_FP_GEN_CNTL,          state->fp_gen_cntl);
+
+	if ((dev_priv->chip_family == CHIP_RS400) ||
+	    (dev_priv->chip_family == CHIP_RS480)) {
+		RADEON_WRITE(RS400_FP_2ND_GEN_CNTL, state->fp_2nd_gen_cntl);
+		/*RADEON_WRITE(RS400_TMDS2_CNTL, state->tmds2_cntl);*/
+		RADEON_WRITE(RS400_TMDS2_TRANSMITTER_CNTL, state->tmds2_transmitter_cntl);
+	}
+
+	/* old AIW Radeon has some BIOS initialization problem
+	 * with display buffer underflow, only occurs to DFP
+	 */
+	if (dev_priv->flags & RADEON_SINGLE_CRTC)
+		RADEON_WRITE(RADEON_GRPH_BUFFER_CNTL,
+			     RADEON_READ(RADEON_GRPH_BUFFER_CNTL) & ~0x7f0000);
+
+}
+
+/* Write FP2 registers */
+void radeon_restore_fp2_registers(struct drm_device *dev, struct radeon_legacy_state *state)
+{
+	struct drm_radeon_private *dev_priv = dev->dev_private;
+	RADEON_WRITE(RADEON_FP2_GEN_CNTL, state->fp2_gen_cntl);
+
+	if ((dev_priv->chip_family == CHIP_RS400) ||
+	    (dev_priv->chip_family == CHIP_RS480))
+		RADEON_WRITE(RS400_FP2_2_GEN_CNTL, state->fp2_2_gen_cntl);
+}
+
+/* Write RMX registers */
+void radeon_state_rmx_registers(struct drm_device *dev, struct radeon_legacy_state *state)
+{
+	struct drm_radeon_private *dev_priv = dev->dev_private;
+	RADEON_WRITE(RADEON_FP_HORZ_STRETCH,      state->fp_horz_stretch);
+	RADEON_WRITE(RADEON_FP_VERT_STRETCH,      state->fp_vert_stretch);
+	RADEON_WRITE(RADEON_CRTC_MORE_CNTL,       state->crtc_more_cntl);
+	RADEON_WRITE(RADEON_FP_HORZ_VERT_ACTIVE,  state->fp_horz_vert_active);
+	RADEON_WRITE(RADEON_FP_H_SYNC_STRT_WID,   state->fp_h_sync_strt_wid);
+	RADEON_WRITE(RADEON_FP_V_SYNC_STRT_WID,   state->fp_v_sync_strt_wid);
+	RADEON_WRITE(RADEON_FP_CRTC_H_TOTAL_DISP, state->fp_crtc_h_total_disp);
+	RADEON_WRITE(RADEON_FP_CRTC_V_TOTAL_DISP, state->fp_crtc_v_total_disp);
+
+}
+
+/* Write LVDS registers */
+void radeon_restore_lvds_registers(struct drm_device *dev, struct radeon_legacy_state *state)
+{
+	struct drm_radeon_private *dev_priv = dev->dev_private;
+
+	if (dev_priv->flags & RADEON_IS_MOBILITY) {
+		RADEON_WRITE(RADEON_LVDS_GEN_CNTL,  state->lvds_gen_cntl);
+		/*RADEON_WRITE(RADEON_LVDS_PLL_CNTL,  state->lvds_pll_cntl);*/
+
+		if (dev_priv->chip_family == CHIP_RV410) {
+			RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, 0);
+		}
+	}
+
+}
+
+static void radeon_init_fp_registers(struct drm_encoder *encoder, struct drm_display_mode *mode,
+				     bool is_primary)
+{
+	
+
+}
+
+static void radeon_init_dac_registers(struct drm_encoder *encoder, struct radeon_legacy_state *state,
+				      struct drm_display_mode *mode, bool is_primary)
+{
+	struct drm_device *dev = encoder->dev;
+	struct drm_radeon_private *dev_priv = dev->dev_private;
+
+	if (is_primary) {
+		if (dev_priv->chip_family == CHIP_R200 || radeon_is_r300(dev_priv)) {
+			state->disp_output_cntl = RADEON_READ(RADEON_DISP_OUTPUT_CNTL &
+							      ~RADEON_DISP_DAC_SOURCE_MASK);
+		} else {
+			state->dac2_cntl = RADEON_READ(RADEON_DAC_CNTL2)  & ~(RADEON_DAC2_DAC_CLK_SEL);
+		}
+	} else {
+		if (dev_priv->chip_family == CHIP_R200 || radeon_is_r300(dev_priv)) {
+			state->disp_output_cntl = RADEON_READ(RADEON_DISP_OUTPUT_CNTL &
+							      ~RADEON_DISP_DAC_SOURCE_MASK);
+			state->disp_output_cntl |= RADEON_DISP_DAC_SOURCE_CRTC2;
+		} else {
+			state->dac2_cntl = RADEON_READ(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC_CLK_SEL;
+		}
+	}
+
+	state->dac_cntl = (RADEON_DAC_MASK_ALL |
+			   RADEON_DAC_VGA_ADR_EN |
+			   /* TODO 6-bits */
+			   RADEON_DAC_8BIT_EN);
+	state->dac_macro_cntl = RADEON_READ(RADEON_DAC_MACRO_CNTL);
+}
+
+static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode)
+{
+	struct drm_device *dev = encoder->dev;
+}
+
+static void radeon_legacy_lvds_prepare(struct drm_encoder *encoder)
+{
+	radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_OFF);
+}
+
+static void radeon_legacy_lvds_commit(struct drm_encoder *encoder)
+{
+	radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_ON);
+}
+
+static void radeon_legacy_lvds_mode_set(struct drm_encoder *encoder,
+				  struct drm_display_mode *mode,
+				  struct drm_display_mode *adjusted_mode)
+{
+
+
+}
+
+static bool radeon_legacy_lvds_mode_fixup(struct drm_encoder *encoder,
+				    struct drm_display_mode *mode,
+				    struct drm_display_mode *adjusted_mode)
+{
+	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+
+	radeon_encoder->flags &= ~RADEON_USE_RMX;
+
+	if (radeon_encoder->rmx_type != RMX_OFF)
+		radeon_rmx_mode_fixup(encoder, mode, adjusted_mode);
+	
+	return true;
+}
+
+static const struct drm_encoder_helper_funcs radeon_legacy_lvds_helper_funcs = {
+	.dpms = radeon_legacy_lvds_dpms,
+	.mode_fixup = radeon_legacy_lvds_mode_fixup,
+	.prepare = radeon_legacy_lvds_prepare,
+	.mode_set = radeon_legacy_lvds_mode_set,
+	.commit = radeon_legacy_lvds_commit,
+};
+
+
+static const struct drm_encoder_funcs radeon_legacy_lvds_enc_funcs = {
+	.destroy = radeon_enc_destroy,
+};
+
+
+struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index)
+{
+	struct drm_radeon_private *dev_priv = dev->dev_private;
+	struct radeon_mode_info *mode_info = &dev_priv->mode_info;
+	struct radeon_encoder *radeon_encoder;
+	struct drm_encoder *encoder;
+	radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
+	if (!radeon_encoder) {
+		return NULL;
+	}
+
+	encoder = &radeon_encoder->base;
+
+	encoder->possible_crtcs = 0x3;
+	encoder->possible_clones = 0;
+	drm_encoder_init(dev, encoder, &radeon_legacy_lvds_enc_funcs,
+			 DRM_MODE_ENCODER_LVDS);
+
+	drm_encoder_helper_add(encoder, &radeon_legacy_lvds_helper_funcs);
+
+	/* TODO get the LVDS info from the BIOS for panel size etc. */
+	/* get the lvds info from the bios */
+	radeon_combios_get_lvds_info(radeon_encoder);
+
+	/* LVDS gets default RMX full scaling */
+	radeon_encoder->rmx_type = RMX_FULL;
+
+	return encoder;
+}
+
+static bool radeon_legacy_primary_dac_mode_fixup(struct drm_encoder *encoder,
+						 struct drm_display_mode *mode,
+						 struct drm_display_mode *adjusted_mode)
+{
+	return true;
+}
+
+static void radeon_legacy_primary_dac_dpms(struct drm_encoder *encoder, int mode)
+{
+
+
+}
+
+static void radeon_legacy_primary_dac_prepare(struct drm_encoder *encoder)
+{
+	radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
+}
+
+static void radeon_legacy_primary_dac_commit(struct drm_encoder *encoder)
+{
+	radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_ON);
+}
+
+static void radeon_legacy_primary_dac_mode_set(struct drm_encoder *encoder,
+				  struct drm_display_mode *mode,
+				  struct drm_display_mode *adjusted_mode)
+{
+	struct drm_device *dev = encoder->dev;
+	struct drm_radeon_private *dev_priv = dev->dev_private;
+	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
+	radeon_init_dac_registers(encoder, &dev_priv->mode_info.legacy_state, adjusted_mode,
+				  (radeon_crtc->crtc_id == 1));
+
+	radeon_restore_dac_registers(dev, &dev_priv->mode_info.legacy_state);
+}
+
+static const struct drm_encoder_helper_funcs radeon_legacy_primary_dac_helper_funcs = {
+	.dpms = radeon_legacy_primary_dac_dpms,
+	.mode_fixup = radeon_legacy_primary_dac_mode_fixup,
+	.prepare = radeon_legacy_primary_dac_prepare,
+	.mode_set = radeon_legacy_primary_dac_mode_set,
+	.commit = radeon_legacy_primary_dac_commit,
+};
+
+
+static const struct drm_encoder_funcs radeon_legacy_primary_dac_enc_funcs = {
+	.destroy = radeon_enc_destroy,
+};
+
+struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int has_tv)
+{
+	struct drm_radeon_private *dev_priv = dev->dev_private;
+	struct radeon_mode_info *mode_info = &dev_priv->mode_info;
+	struct radeon_encoder *radeon_encoder;
+	struct drm_encoder *encoder;
+	radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
+	if (!radeon_encoder) {
+		return NULL;
+	}
+
+	encoder = &radeon_encoder->base;
+
+	encoder->possible_crtcs = 0x3;
+	encoder->possible_clones = 0;
+	drm_encoder_init(dev, encoder, &radeon_legacy_primary_dac_enc_funcs,
+			 DRM_MODE_ENCODER_DAC);
+
+	drm_encoder_helper_add(encoder, &radeon_legacy_primary_dac_helper_funcs);
+
+	return encoder;
+}
+
+
+static bool radeon_legacy_tmds_int_mode_fixup(struct drm_encoder *encoder,
+						 struct drm_display_mode *mode,
+						 struct drm_display_mode *adjusted_mode)
+{
+
+}
+
+static void radeon_legacy_tmds_int_dpms(struct drm_encoder *encoder, int mode)
+{
+	/* dfp1 */
+
+}
+
+static void radeon_legacy_tmds_int_prepare(struct drm_encoder *encoder)
+{
+	radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_OFF);
+}
+
+static void radeon_legacy_tmds_int_commit(struct drm_encoder *encoder)
+{
+	radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_ON);
+}
+
+static void radeon_legacy_tmds_int_mode_set(struct drm_encoder *encoder,
+				  struct drm_display_mode *mode,
+				  struct drm_display_mode *adjusted_mode)
+{
+	
+
+}
+
+static const struct drm_encoder_helper_funcs radeon_legacy_tmds_int_helper_funcs = {
+	.dpms = radeon_legacy_tmds_int_dpms,
+	.mode_fixup = radeon_legacy_tmds_int_mode_fixup,
+	.prepare = radeon_legacy_tmds_int_prepare,
+	.mode_set = radeon_legacy_tmds_int_mode_set,
+	.commit = radeon_legacy_tmds_int_commit,
+};
+
+
+static const struct drm_encoder_funcs radeon_legacy_tmds_int_enc_funcs = {
+	.destroy = radeon_enc_destroy,
+};
+
+struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index)
+{
+	struct drm_radeon_private *dev_priv = dev->dev_private;
+	struct radeon_mode_info *mode_info = &dev_priv->mode_info;
+	struct radeon_encoder *radeon_encoder;
+	struct drm_encoder *encoder;
+	radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
+	if (!radeon_encoder) {
+		return NULL;
+	}
+
+	encoder = &radeon_encoder->base;
+
+	encoder->possible_crtcs = 0x3;
+	encoder->possible_clones = 0;
+	drm_encoder_init(dev, encoder, &radeon_legacy_tmds_int_enc_funcs,
+			 DRM_MODE_ENCODER_TMDS);
+
+	drm_encoder_helper_add(encoder, &radeon_legacy_tmds_int_helper_funcs);
+
+	radeon_combios_get_tmds_info(radeon_encoder);
+	return encoder;
+}
diff --git a/linux-core/radeon_mode.h b/linux-core/radeon_mode.h
index f75e8272..91c6f48d 100644
--- a/linux-core/radeon_mode.h
+++ b/linux-core/radeon_mode.h
@@ -115,6 +115,11 @@ struct radeon_bios_connector {
 	int igp_lane_info;
 };
 
+struct radeon_tmds_pll {
+    uint32_t freq;
+    uint32_t value;
+};
+
 #define RADEON_MAX_BIOS_CONNECTOR 16
 	
 #define RADEON_PLL_USE_BIOS_DIVS   (1 << 0)
@@ -124,27 +129,177 @@ struct radeon_bios_connector {
 #define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4)
 
 struct radeon_pll {
-    uint16_t          reference_freq;
-    uint16_t          reference_div;
-    uint32_t          pll_in_min;
-    uint32_t          pll_in_max;
-    uint32_t          pll_out_min;
-    uint32_t          pll_out_max;
-    uint16_t          xclk;
-
-    uint32_t          min_ref_div;
-    uint32_t          max_ref_div;
-    uint32_t          min_post_div;
-    uint32_t          max_post_div;
-    uint32_t          min_feedback_div;
-    uint32_t          max_feedback_div;
-    uint32_t          best_vco;
+	uint16_t reference_freq;
+	uint16_t reference_div;
+	uint32_t pll_in_min;
+	uint32_t pll_in_max;
+	uint32_t pll_out_min;
+	uint32_t pll_out_max;
+	uint16_t xclk;
+
+	uint32_t min_ref_div;
+	uint32_t max_ref_div;
+	uint32_t min_post_div;
+	uint32_t max_post_div;
+	uint32_t min_feedback_div;
+	uint32_t max_feedback_div;
+	uint32_t best_vco;
+};
+
+#define MAX_H_CODE_TIMING_LEN 32
+#define MAX_V_CODE_TIMING_LEN 32
+
+struct radeon_legacy_state {
+
+	uint32_t bus_cntl;
+
+	/* DAC */
+	uint32_t dac_cntl;
+	uint32_t dac2_cntl;
+	uint32_t dac_macro_cntl;
+
+	/* CRTC 1 */
+	uint32_t crtc_gen_cntl;
+	uint32_t crtc_ext_cntl;
+	uint32_t crtc_h_total_disp;
+	uint32_t crtc_h_sync_strt_wid;
+	uint32_t crtc_v_total_disp;
+	uint32_t crtc_v_sync_strt_wid;
+	uint32_t crtc_offset;
+	uint32_t crtc_offset_cntl;
+	uint32_t crtc_pitch;
+	uint32_t disp_merge_cntl;
+	uint32_t grph_buffer_cntl;
+	uint32_t crtc_more_cntl;
+	uint32_t crtc_tile_x0_y0;
+
+	/* CRTC 2 */
+	uint32_t crtc2_gen_cntl;
+	uint32_t crtc2_h_total_disp;
+	uint32_t crtc2_h_sync_strt_wid;
+	uint32_t crtc2_v_total_disp;
+	uint32_t crtc2_v_sync_strt_wid;
+	uint32_t crtc2_offset;
+	uint32_t crtc2_offset_cntl;
+	uint32_t crtc2_pitch;
+	uint32_t crtc2_tile_x0_y0;
+
+	uint32_t disp_output_cntl;
+	uint32_t disp_tv_out_cntl;
+	uint32_t disp_hw_debug;
+	uint32_t disp2_merge_cntl;
+	uint32_t grph2_buffer_cntl;
+
+	/* FP regs */
+	uint32_t fp_crtc_h_total_disp;
+	uint32_t fp_crtc_v_total_disp;
+	uint32_t fp_gen_cntl;
+	uint32_t fp2_gen_cntl;
+	uint32_t fp_h_sync_strt_wid;
+	uint32_t fp_h2_sync_strt_wid;
+	uint32_t fp_horz_stretch;
+	uint32_t fp_horz_vert_active;
+	uint32_t fp_panel_cntl;
+	uint32_t fp_v_sync_strt_wid;
+	uint32_t fp_v2_sync_strt_wid;
+	uint32_t fp_vert_stretch;
+	uint32_t lvds_gen_cntl;
+	uint32_t lvds_pll_cntl;
+	uint32_t tmds_pll_cntl;
+	uint32_t tmds_transmitter_cntl;
+
+	/* Computed values for PLL */
+	uint32_t dot_clock_freq;
+	uint32_t pll_output_freq;
+	int  feedback_div;
+	int  reference_div;
+	int  post_div;
+
+	/* PLL registers */
+	uint32_t ppll_ref_div;
+	uint32_t ppll_div_3;
+	uint32_t htotal_cntl;
+	uint32_t vclk_ecp_cntl;
+
+	/* Computed values for PLL2 */
+	uint32_t dot_clock_freq_2;
+	uint32_t pll_output_freq_2;
+	int feedback_div_2;
+	int reference_div_2;
+	int post_div_2;
+
+	/* PLL2 registers */
+	uint32_t p2pll_ref_div;
+	uint32_t p2pll_div_0;
+	uint32_t htotal_cntl2;
+	uint32_t pixclks_cntl;
+
+	bool palette_valid;
+	uint32_t palette[256];
+	uint32_t palette2[256];
+
+	uint32_t disp2_req_cntl1;
+	uint32_t disp2_req_cntl2;
+	uint32_t dmif_mem_cntl1;
+	uint32_t disp1_req_cntl1;
+
+	uint32_t fp_2nd_gen_cntl;
+	uint32_t fp2_2_gen_cntl;
+	uint32_t tmds2_cntl;
+	uint32_t tmds2_transmitter_cntl;
+
+	/* TV out registers */
+	uint32_t tv_master_cntl;
+	uint32_t tv_htotal;
+	uint32_t tv_hsize;
+	uint32_t tv_hdisp;
+	uint32_t tv_hstart;
+	uint32_t tv_vtotal;
+	uint32_t tv_vdisp;
+	uint32_t tv_timing_cntl;
+	uint32_t tv_vscaler_cntl1;
+	uint32_t tv_vscaler_cntl2;
+	uint32_t tv_sync_size;
+	uint32_t tv_vrestart;
+	uint32_t tv_hrestart;
+	uint32_t tv_frestart;
+	uint32_t tv_ftotal;
+	uint32_t tv_clock_sel_cntl;
+	uint32_t tv_clkout_cntl;
+	uint32_t tv_data_delay_a;
+	uint32_t tv_data_delay_b;
+	uint32_t tv_dac_cntl;
+	uint32_t tv_pll_cntl;
+	uint32_t tv_pll_cntl1;
+	uint32_t tv_pll_fine_cntl;
+	uint32_t tv_modulator_cntl1;
+	uint32_t tv_modulator_cntl2;
+	uint32_t tv_frame_lock_cntl;
+	uint32_t tv_pre_dac_mux_cntl;
+	uint32_t tv_rgb_cntl;
+	uint32_t tv_y_saw_tooth_cntl;
+	uint32_t tv_y_rise_cntl;
+	uint32_t tv_y_fall_cntl;
+	uint32_t tv_uv_adr;
+	uint32_t tv_upsamp_and_gain_cntl;
+	uint32_t tv_gain_limit_settings;
+	uint32_t tv_linear_gain_settings;
+	uint32_t tv_crc_cntl;
+	uint32_t tv_sync_cntl;
+	uint32_t gpiopad_a;
+	uint32_t pll_test_cntl;
+
+	uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN];
+	uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN];
+
+
 };
 
 struct radeon_mode_info {
 	struct atom_context *atom_context;
 	struct radeon_bios_connector bios_connector[RADEON_MAX_BIOS_CONNECTOR];
 	struct radeon_pll pll;
+	struct radeon_legacy_state legacy_state;
 };
 
 struct radeon_crtc {
@@ -185,6 +340,7 @@ struct radeon_encoder {
 	uint32_t vblank;
 	uint32_t panel_pwr_delay;
 	uint32_t dotclock;
+	struct radeon_tmds_pll tmds_pll[4];
 };
 
 struct radeon_connector {
@@ -221,6 +377,8 @@ struct drm_encoder *radeon_encoder_lvtma_add(struct drm_device *dev, int bios_in
 struct drm_encoder *radeon_encoder_atom_dac_add(struct drm_device *dev, int bios_index, int dac_id, int with_tv);
 struct drm_encoder *radeon_encoder_atom_tmds_add(struct drm_device *dev, int bios_index, int tmds_type);
 struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index);
+struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv);
+struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index);
 
 extern void radeon_crtc_load_lut(struct drm_crtc *crtc);
 extern void atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y);
@@ -233,6 +391,7 @@ extern bool radeon_atom_get_clock_info(struct drm_device *dev);
 extern bool radeon_combios_get_clock_info(struct drm_device *dev);
 extern void radeon_get_lvds_info(struct radeon_encoder *encoder);
 extern bool radeon_combios_get_lvds_info(struct radeon_encoder *encoder);
+extern bool radeon_combios_get_tmds_info(struct radeon_encoder *encoder);
 extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
 				     u16 blue, int regno);
 struct drm_framebuffer *radeon_user_framebuffer_create(struct drm_device *dev,
@@ -245,6 +404,8 @@ int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev);
 void radeon_atombios_init_crtc(struct drm_device *dev,
 			       struct radeon_crtc *radeon_crtc);
+void radeon_legacy_init_crtc(struct drm_device *dev,
+			     struct radeon_crtc *radeon_crtc);
 void avivo_i2c_do_lock(struct radeon_connector *radeon_connector, int lock_state);
 
 void radeon_atom_static_pwrmgt_setup(struct drm_device *dev, int enable);
@@ -252,4 +413,9 @@ void radeon_atom_dyn_clk_setup(struct drm_device *dev, int enable);
 void radeon_get_clock_info(struct drm_device *dev);
 extern bool radeon_get_atom_connector_info_from_bios_connector_table(struct drm_device *dev);
 
+void radeon_rmx_mode_fixup(struct drm_encoder *encoder,
+			   struct drm_display_mode *mode,
+			   struct drm_display_mode *adjusted_mode);
+void radeon_enc_destroy(struct drm_encoder *encoder);
+
 #endif
diff --git a/shared-core/radeon_cp.c b/shared-core/radeon_cp.c
index 4c03f739..b751740c 100644
--- a/shared-core/radeon_cp.c
+++ b/shared-core/radeon_cp.c
@@ -2282,6 +2282,7 @@ static void radeon_set_dynamic_clock(struct drm_device *dev, int mode)
 int radeon_modeset_cp_init(struct drm_device *dev)
 {
 	drm_radeon_private_t *dev_priv = dev->dev_private;
+	uint32_t tmp;
 
 	/* allocate a ring and ring rptr bits from GART space */
 	/* these are allocated in GEM files */
@@ -2311,6 +2312,11 @@ int radeon_modeset_cp_init(struct drm_device *dev)
 
 	radeon_cp_init_ring_buffer(dev, dev_priv);
 
+	/* need to enable BUS mastering in Buscntl */
+	tmp = RADEON_READ(RADEON_BUS_CNTL);
+	tmp &= ~RADEON_BUS_MASTER_DIS;
+	RADEON_WRITE(RADEON_BUS_CNTL, tmp);
+
 	radeon_do_engine_reset(dev);
 	radeon_test_writeback(dev_priv);
 
@@ -2381,8 +2387,8 @@ int radeon_modeset_preinit(struct drm_device *dev)
 
 	if (dev_priv->is_atom_bios) {
 		dev_priv->mode_info.atom_context = atom_parse(&card, dev_priv->bios);
-		radeon_get_clock_info(dev);
 	}
+	radeon_get_clock_info(dev);
 	return 0;
 }
 
diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h
index 94975e4d..51a5b00c 100644
--- a/shared-core/radeon_drv.h
+++ b/shared-core/radeon_drv.h
@@ -1277,41 +1277,59 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
 extern int RADEON_READ_PLL(struct drm_radeon_private *dev_priv, int addr);
 extern void RADEON_WRITE_PLL(struct drm_radeon_private *dev_priv, int addr, uint32_t data);
 
-#define RADEON_WRITE_PCIE( addr, val )					\
+#define RADEON_WRITE_P(reg, val, mask)		\
+do {						\
+	uint32_t tmp = RADEON_READ(reg);	\
+	tmp &= ~(mask);				\
+	tmp |= ((val) & ~(mask));		\
+	RADEON_WRITE(reg, tmp);			\
+} while(0)
+
+#define RADEON_WRITE_PLL_P(dev_priv, addr, val, mask)		\
+do {								\
+	uint32_t tmp_ = RADEON_READ_PLL(dev_priv, addr);	\
+	tmp_ &= (mask);						\
+	tmp_ |= ((val) & ~(mask));				\
+	RADEON_WRITE_PLL(dev_priv, addr, tmp_);			\
+} while (0)
+
+
+
+#define RADEON_WRITE_PCIE(addr, val)					\
 do {									\
-	RADEON_WRITE8( RADEON_PCIE_INDEX,				\
+	RADEON_WRITE8(RADEON_PCIE_INDEX,				\
 			((addr) & 0xff));				\
-	RADEON_WRITE( RADEON_PCIE_DATA, (val) );			\
+	RADEON_WRITE(RADEON_PCIE_DATA, (val));			\
 } while (0)
 
-#define R500_WRITE_MCIND( addr, val )					\
+#define R500_WRITE_MCIND(addr, val)					\
 do {								\
 	RADEON_WRITE(R520_MC_IND_INDEX, 0xff0000 | ((addr) & 0xff));	\
 	RADEON_WRITE(R520_MC_IND_DATA, (val));			\
 	RADEON_WRITE(R520_MC_IND_INDEX, 0);	\
 } while (0)
 
-#define RS480_WRITE_MCIND( addr, val )				\
+#define RS480_WRITE_MCIND(addr, val)				\
 do {									\
-	RADEON_WRITE( RS480_NB_MC_INDEX,				\
+	RADEON_WRITE(RS480_NB_MC_INDEX,				\
 			((addr) & 0xff) | RS480_NB_MC_IND_WR_EN);	\
-	RADEON_WRITE( RS480_NB_MC_DATA, (val) );			\
-	RADEON_WRITE( RS480_NB_MC_INDEX, 0xff );			\
+	RADEON_WRITE(RS480_NB_MC_DATA, (val));			\
+	RADEON_WRITE(RS480_NB_MC_INDEX, 0xff);			\
 } while (0)
 
-#define RS690_WRITE_MCIND( addr, val )					\
+#define RS690_WRITE_MCIND(addr, val)					\
 do {								\
 	RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_EN | ((addr) & RS690_MC_INDEX_MASK));	\
 	RADEON_WRITE(RS690_MC_DATA, val);			\
 	RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK);	\
 } while (0)
 
-#define IGP_WRITE_MCIND( addr, val )				\
+#define IGP_WRITE_MCIND(addr, val)				\
 do {									\
-        if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)       \
-	        RS690_WRITE_MCIND( addr, val );                         \
-	else                                                            \
-	        RS480_WRITE_MCIND( addr, val );                         \
+	if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)       \
+		RS690_WRITE_MCIND(addr, val);				\
+	else								\
+		RS480_WRITE_MCIND(addr, val);				\
 } while (0)
 
 #define CP_PACKET0( reg, n )						\
@@ -1355,42 +1373,42 @@ do {									\
 
 #define RADEON_FLUSH_CACHE() do {					\
 	if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {	\
-	        OUT_RING( CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 0 ) ); \
-	        OUT_RING( RADEON_RB3D_DC_FLUSH );			\
+		OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));	\
+		OUT_RING(RADEON_RB3D_DC_FLUSH);				\
 	} else {                                                        \
-	        OUT_RING( CP_PACKET0( R300_RB3D_DSTCACHE_CTLSTAT, 0 ) ); \
-	        OUT_RING( RADEON_RB3D_DC_FLUSH );			\
-        }                                                               \
+		OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));	\
+		OUT_RING(RADEON_RB3D_DC_FLUSH);				\
+	}                                                               \
 } while (0)
 
 #define RADEON_PURGE_CACHE() do {					\
 	if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {	\
-	        OUT_RING( CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 0 ) ); \
-	        OUT_RING( RADEON_RB3D_DC_FLUSH_ALL );			\
+		OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));	\
+		OUT_RING(RADEON_RB3D_DC_FLUSH_ALL);			\
 	} else {                                                        \
-	        OUT_RING( CP_PACKET0( R300_RB3D_DSTCACHE_CTLSTAT, 0 ) ); \
-	        OUT_RING( RADEON_RB3D_DC_FLUSH_ALL );			\
-        }                                                               \
+		OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));	\
+		OUT_RING(RADEON_RB3D_DC_FLUSH_ALL);			\
+	}                                                               \
 } while (0)
 
 #define RADEON_FLUSH_ZCACHE() do {					\
 	if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {	\
-	        OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \
-	        OUT_RING( RADEON_RB3D_ZC_FLUSH );			\
+		OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));	\
+		OUT_RING(RADEON_RB3D_ZC_FLUSH);				\
 	} else {                                                        \
-	        OUT_RING( CP_PACKET0( R300_ZB_ZCACHE_CTLSTAT, 0 ) );	\
-	        OUT_RING( R300_ZC_FLUSH );				\
-        }                                                               \
+		OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0));	\
+		OUT_RING(R300_ZC_FLUSH);				\
+	}                                                               \
 } while (0)
 
 #define RADEON_PURGE_ZCACHE() do {					\
 	if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {	\
-	        OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \
-	        OUT_RING( RADEON_RB3D_ZC_FLUSH_ALL );			\
+		OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));	\
+		OUT_RING(RADEON_RB3D_ZC_FLUSH_ALL);			\
 	} else {                                                        \
-	        OUT_RING( CP_PACKET0( R300_RB3D_ZCACHE_CTLSTAT, 0 ) ); \
-	        OUT_RING( R300_ZC_FLUSH_ALL );				\
-        }                                                               \
+		OUT_RING(CP_PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));	\
+		OUT_RING(R300_ZC_FLUSH_ALL);				\
+	}                                                               \
 } while (0)
 
 /* ================================================================
@@ -1411,7 +1429,7 @@ do {									\
 #define VB_AGE_TEST_WITH_RETURN( dev_priv )				\
 do {									\
 	struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;		\
-	drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv;		\
+	drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv;	\
 	if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) {		\
 		int __ret = radeon_do_cp_idle( dev_priv );		\
 		if ( __ret ) return __ret;				\
@@ -1587,6 +1605,23 @@ static inline int radeon_update_breadcrumb(struct drm_device *dev)
 
 #define radeon_is_dce3(dev_priv) ((dev_priv->chip_family >= CHIP_RV620))
 
+#define radeon_is_rv100(dev_priv) ((dev_priv->chip_family == CHIP_RV100) || \
+				   (dev_priv->chip_family == CHIP_RV200) || \
+				   (dev_priv->chip_family == CHIP_RS100) || \
+				   (dev_priv->chip_family == CHIP_RS200) || \
+				   (dev_priv->chip_family == CHIP_RV250) || \
+				   (dev_priv->chip_family == CHIP_RV280) || \
+				   (dev_priv->chip_family == CHIP_RS300))
+
+#define radeon_is_r300(dev_priv) ((dev_priv->chip_family == CHIP_R300)  || \
+				  (dev_priv->chip_family == CHIP_RV350) || \
+				  (dev_priv->chip_family == CHIP_R350)  || \
+				  (dev_priv->chip_family == CHIP_RV380) || \
+				  (dev_priv->chip_family == CHIP_R420)  || \
+				  (dev_priv->chip_family == CHIP_RV410) || \
+				  (dev_priv->chip_family == CHIP_RS400) || \
+				  (dev_priv->chip_family == CHIP_RS480))
+
 #define radeon_bios8(dev_priv, v) (dev_priv->bios[v])
 #define radeon_bios16(dev_priv, v) (dev_priv->bios[v] | (dev_priv->bios[(v) + 1] << 8))
 #define radeon_bios32(dev_priv, v) ((dev_priv->bios[v]) | \
@@ -1594,6 +1629,7 @@ static inline int radeon_update_breadcrumb(struct drm_device *dev)
 				    (dev_priv->bios[(v) + 2] << 16) | \
 				    (dev_priv->bios[(v) + 3] << 24))
 
+extern void radeon_pll_errata_after_index(struct drm_radeon_private *dev_priv);
 extern int radeon_emit_irq(struct drm_device * dev);
 
 extern void radeon_gem_free_object(struct drm_gem_object *obj);