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authorKeith Packard <keithp@keithp.com>2008-05-12 13:00:55 -0700
committerKeith Packard <keithp@keithp.com>2008-05-12 13:00:55 -0700
commit6950b7da7157d4d775fc09c7bc31fb0e769c4249 (patch)
tree018f6aa548b4fc510f27e670bd3f4a9808be081e
parentff39db099b9ca6c8feee68101a2269345b7bd798 (diff)
[gem] Clarify use of explicit domain control. Remove Gen3 from I-cache usage.
-rw-r--r--linux-core/drm-gem.txt12
1 files changed, 9 insertions, 3 deletions
diff --git a/linux-core/drm-gem.txt b/linux-core/drm-gem.txt
index 8f95c206..bef437d8 100644
--- a/linux-core/drm-gem.txt
+++ b/linux-core/drm-gem.txt
@@ -358,6 +358,12 @@ to be generally true, this ioctl may be simplified further.
necessary CPU flushing will occur and the object will be correctly
synchronized with the GPU.
+ Note that this synchronization is not required for any accesses
+ going through the driver itself. The pread, pwrite and execbuffer
+ ioctls all perform the necessary domain management internally.
+ Explicit synchronization is only necessary when accessing the object
+ through the mmap'd address.
+
7. Execution (Intel specific)
Managing the command buffers is inherently chip-specific, so the core of gem
@@ -475,9 +481,9 @@ to synchronize what is needed while leaving other cache contents intact.
needs to be flushed to the GPU.
* DRM_GEM_DOMAIN_I915_INSTRUCTION
- Fragment programs on Gen3 and all of the programs on later
- chips use an instruction cache to speed program execution. It must be
- explicitly flushed when new programs are written to memory by the CPU.
+ All of the programs on Gen4 and later chips use an instruction cache to
+ speed program execution. It must be explicitly flushed when new programs
+ are written to memory by the CPU.
* DRM_GEM_DOMAIN_I915_VERTEX
Vertex data uses two different vertex caches, but they're