diff options
| author | Roland Scheidegger <rscheidegger_lists@hispeed.ch> | 2005-01-26 14:19:24 +0000 |
|---|---|---|
| committer | Roland Scheidegger <rscheidegger_lists@hispeed.ch> | 2005-01-26 14:19:24 +0000 |
| commit | 408376b2031cf301f1a8e35e89ceefc72f2fdc94 (patch) | |
| tree | cb7802545105fee0e58f2e28547018cf43abc9e3 | |
| parent | 310abb39b24159be9839156b4034426cea6a7449 (diff) | |
replace magic number with macro constant RADEON_ZBLOCK16
| -rw-r--r-- | shared-core/radeon_cp.c | 3 | ||||
| -rw-r--r-- | shared-core/radeon_drv.h | 1 | ||||
| -rw-r--r-- | shared-core/radeon_state.c | 1 | ||||
| -rw-r--r-- | shared/radeon_cp.c | 3 | ||||
| -rw-r--r-- | shared/radeon_drv.h | 1 | ||||
| -rw-r--r-- | shared/radeon_state.c | 1 |
6 files changed, 6 insertions, 4 deletions
diff --git a/shared-core/radeon_cp.c b/shared-core/radeon_cp.c index 3b3604ba..fdba7c70 100644 --- a/shared-core/radeon_cp.c +++ b/shared-core/radeon_cp.c @@ -1336,7 +1336,8 @@ static int radeon_do_init_cp(drm_device_t * dev, drm_radeon_init_t * init) */ dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE | (dev_priv->color_fmt << 10) | - (1 << 15)); + (dev_priv->microcode_version == UCODE_R100 ? + RADEON_ZBLOCK16 : 0)); dev_priv->depth_clear.rb3d_zstencilcntl = (dev_priv->depth_fmt | diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h index cd75bc17..30c3bcb6 100644 --- a/shared-core/radeon_drv.h +++ b/shared-core/radeon_drv.h @@ -468,6 +468,7 @@ extern void radeon_driver_free_filp_priv(drm_device_t * dev, # define RADEON_ROP_ENABLE (1 << 6) # define RADEON_STENCIL_ENABLE (1 << 7) # define RADEON_Z_ENABLE (1 << 8) +# define RADEON_ZBLOCK16 (1 << 15) #define RADEON_RB3D_DEPTHOFFSET 0x1c24 #define RADEON_RB3D_DEPTHCLEARVALUE 0x3230 #define RADEON_RB3D_DEPTHPITCH 0x1c28 diff --git a/shared-core/radeon_state.c b/shared-core/radeon_state.c index e0d64a2a..86ed132c 100644 --- a/shared-core/radeon_state.c +++ b/shared-core/radeon_state.c @@ -999,7 +999,6 @@ static void radeon_cp_dispatch_clear(drm_device_t * dev, tempRE_CNTL = 0; tempRB3D_CNTL = depth_clear->rb3d_cntl; - tempRB3D_CNTL &= ~(1 << 15); /* unset radeon magic flag */ tempRB3D_ZSTENCILCNTL = depth_clear->rb3d_zstencilcntl; tempRB3D_STENCILREFMASK = 0x0; diff --git a/shared/radeon_cp.c b/shared/radeon_cp.c index 5d13f479..5e23452b 100644 --- a/shared/radeon_cp.c +++ b/shared/radeon_cp.c @@ -1343,7 +1343,8 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init ) */ dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE | (dev_priv->color_fmt << 10) | - (1<<15)); + (dev_priv->microcode_version == UCODE_R100 ? + RADEON_ZBLOCK16 : 0)); dev_priv->depth_clear.rb3d_zstencilcntl = (dev_priv->depth_fmt | diff --git a/shared/radeon_drv.h b/shared/radeon_drv.h index 9e0e8fed..60252db1 100644 --- a/shared/radeon_drv.h +++ b/shared/radeon_drv.h @@ -411,6 +411,7 @@ extern void radeon_driver_irq_uninstall( drm_device_t *dev ); # define RADEON_ROP_ENABLE (1 << 6) # define RADEON_STENCIL_ENABLE (1 << 7) # define RADEON_Z_ENABLE (1 << 8) +# define RADEON_ZBLOCK16 (1 << 15) #define RADEON_RB3D_DEPTHOFFSET 0x1c24 #define RADEON_RB3D_DEPTHCLEARVALUE 0x3230 #define RADEON_RB3D_DEPTHPITCH 0x1c28 diff --git a/shared/radeon_state.c b/shared/radeon_state.c index caba6a3a..66efb5c8 100644 --- a/shared/radeon_state.c +++ b/shared/radeon_state.c @@ -953,7 +953,6 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev, tempRE_CNTL = 0; tempRB3D_CNTL = depth_clear->rb3d_cntl; - tempRB3D_CNTL &= ~(1<<15); /* unset radeon magic flag */ tempRB3D_ZSTENCILCNTL = depth_clear->rb3d_zstencilcntl; tempRB3D_STENCILREFMASK = 0x0; |