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authorBen Skeggs <skeggsb@gmail.com>2008-05-02 01:36:30 +1000
committerBen Skeggs <skeggsb@gmail.com>2008-05-02 01:36:30 +1000
commit3ac74f3208ed15a990a0a26742fbfe566f08aa80 (patch)
tree556dccc0680c2cf2b540a1f189ffc6267c986ffe
parent6d8062ac1e048c3643d3a9d2432e497e17f717de (diff)
nv50: enable 0x400500 bit 0 after PGRAPH exception also
No solid idea about what these 2 bits do, but nv50 can now survive a few PGRAPH exceptions just as nv40 does :)
-rw-r--r--shared-core/nouveau_irq.c8
1 files changed, 6 insertions, 2 deletions
diff --git a/shared-core/nouveau_irq.c b/shared-core/nouveau_irq.c
index d002f642..2a3d8a0b 100644
--- a/shared-core/nouveau_irq.c
+++ b/shared-core/nouveau_irq.c
@@ -475,8 +475,12 @@ nv50_pgraph_irq_handler(struct drm_device *dev)
NV_WRITE(NV03_PGRAPH_INTR, status);
}
- if ((NV_READ(0x400500) & (1 << 16)) == 0)
- NV_WRITE(0x400500, NV_READ(0x400500) | (1 << 16));
+ {
+ const int isb = (1 << 16) | (1 << 0);
+
+ if ((NV_READ(0x400500) & isb) != isb)
+ NV_WRITE(0x400500, NV_READ(0x400500) | isb);
+ }
NV_WRITE(NV03_PMC_INTR_0, NV_PMC_INTR_0_PGRAPH_PENDING);
}